公开(公告)号：US07528644B2

公开(公告)日：2009-05-05

申请号：US11482448

申请日：2006-07-07

申请人： Jong-Hyun Choi ,  Dong-Il Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo

IPC分类号： H01L35/00

CPC分类号： G01K7/015 ,  G01K2219/00

摘要： A temperature detecting circuit is provided. The temperature detecting circuit includes a reference and detection voltage generator for generating a reference voltage corresponding to a first and a second reference current, and changing first to M-th (M being a natural number) detection currents based on first to M-th temperature detection codes to generate first to M-th detection voltages corresponding to the changed first to M-th detection currents and the second reference current; a temperature detection signal generator for comparing each of the first to M-th detection voltages with the reference voltage to generate first to M-th temperature detection signals; and a temperature detection controller for detecting an operation temperature of a semiconductor device while changing the first to M-th temperature detection codes in response to the first to M-th temperature detection signals from the temperature detection signal generator.

摘要翻译： 提供温度检测电路。 温度检测电路包括用于产生对应于第一和第二参考电流的参考电压的参考和检测电压发生器，并且基于第一至第M温度首先改变为第M（M为自然数）检测电流 检测码，用于产生对应于改变的第一至第M检测电流和第二参考电流的第一至第M检测电压; 温度检测信号发生器，用于将第一至第M检测电压中的每一个与参考电压进行比较，以产生第一至第M温度检测信号; 以及温度检测控制器，用于响应于来自温度检测信号发生器的第一至第M温度检测信号，在改变第一至第M温度检测代码的同时检测半导体器件的工作温度。

公开(公告)号：US07408826B2

公开(公告)日：2008-08-05

申请号：US11489440

申请日：2006-07-20

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Nam-Jong Kim

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Nam-Jong Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  H01L29/785

摘要： A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.

摘要翻译： 一种半导体存储器件，包括存储单元阵列，该存储单元阵列具有连接在位线对之间的多个存储单元，所述位线对向位线对传送数据;预充电电路，用于在位置线对期间预充电电压电平 预充电周期和连接在位线对之间的一个或多个位线读出放大器，并检测位线对的电压差以放大位线对的电平。 半导体存储器件包括一个或多个FINFET。

公开(公告)号：US20070098042A1

公开(公告)日：2007-05-03

申请号：US11482448

申请日：2006-07-07

申请人： Jong-Hyun Choi ,  Dong-Il Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo

IPC分类号： G01K7/00

CPC分类号： G01K7/015 ,  G01K2219/00

摘要： A temperature detecting circuit is provided. The temperature detecting circuit includes a reference and detection voltage generator for generating a reference voltage corresponding to a first and a second reference current, and changing first to M-th (M being a natural number) detection currents based on first to M-th temperature detection codes to generate first to M-th detection voltages corresponding to the changed first to M-th detection currents and the second reference current; a temperature detection signal generator for comparing each of the first to M-th detection voltages with the reference voltage to generate first to M-th temperature detection signals; and a temperature detection controller for detecting an operation temperature of a semiconductor device while changing the first to M-th temperature detection codes in response to the first to M-th temperature detection signals from the temperature detection signal generator.

摘要翻译： 提供温度检测电路。 温度检测电路包括用于产生对应于第一和第二参考电流的参考电压的参考和检测电压发生器，并且基于第一至第M温度首先改变为第M（M为自然数）检测电流 检测码，用于产生对应于改变的第一至第M检测电流和第二参考电流的第一至第M检测电压; 温度检测信号发生器，用于将第一至第M检测电压中的每一个与参考电压进行比较，以产生第一至第M温度检测信号; 以及温度检测控制器，用于响应于来自温度检测信号发生器的第一至第M温度检测信号，在改变第一至第M温度检测代码的同时检测半导体器件的工作温度。

公开(公告)号：US20070047357A1

公开(公告)日：2007-03-01

申请号：US11489440

申请日：2006-07-20

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Nam-Jong Kim

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Nam-Jong Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  H01L29/785

摘要： A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.

摘要翻译： 一种半导体存储器件，包括存储单元阵列，该存储单元阵列具有连接在位线对之间的多个存储单元，所述位线对向位线对传送数据;预充电电路，用于将位线对预充电到预充电电压电平 预充电周期和连接在位线对之间的一个或多个位线读出放大器，并检测位线对的电压差以放大位线对的电平。 半导体存储器件包括一个或多个FINFET。

公开(公告)号：US07843752B2

公开(公告)日：2010-11-30

申请号：US12111468

申请日：2008-04-29

申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： G11C7/04

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US20090046531A1

公开(公告)日：2009-02-19

申请号：US12111468

申请日：2008-04-29

申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： G11C7/04

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US20060176079A1

公开(公告)日：2006-08-10

申请号：US11348582

申请日：2006-02-06

申请人： Jong-Hyun Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Young-Hun Seo

IPC分类号： H03K19/0175

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/0005

摘要： An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.

摘要翻译： 一种用于半导体存储器件的输入/输出电路，包括数据输出电路，配置为响应于输入/输出使能信号缓冲半导体存储器件中的输出数据，以将缓冲的输出数据输出到输入/输出信号线， 数据输入电路，被配置为从输入/输出信号线接收输入数据并缓冲输入数据以将缓冲的输入数据传送到半导体存储器件;以及负载控制器，被配置为响应于控制输入/输出信号线上的负载 到输入/输出使能信号。

公开(公告)号：US20140016424A1

公开(公告)日：2014-01-16

申请号：US14017080

申请日：2013-09-03

申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： G11C11/402

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US08218137B2

公开(公告)日：2012-07-10

申请号：US12941500

申请日：2010-11-08

申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： G11C7/00

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US07394290B2

公开(公告)日：2008-07-01

申请号：US11422856

申请日：2006-06-07

申请人： Young-Hun Seo ,  Jong-Hyun Choi

发明人： Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： H03K19/0175

CPC分类号： H03K19/0016

摘要： A semiconductor integrated circuit with low power consumption is provided. In one embodiment, the semiconductor integrated circuit includes a logic circuit portion that is connected between a first power line and a virtual ground line. The logic circuit portion includes at least one NMOS transistor having a first threshold voltage and at least one PMOS transistor having a second threshold voltage. The semiconductor integrated circuit further includes a first MOS transistor, which is connected between the virtual ground line and a ground voltage, where the first MOS transistor has the first threshold voltage and applies the ground voltage to the virtual ground line in an active state. Also included in the semiconductor integrated circuit is a controller that is connected to the first MOS transistor, where the controller applies the ground voltage to the first MOS transistor in the active state and applies a bulk voltage supplied from a bulk power line in a standby state to control a threshold voltage of the first MOS transistor.

摘要翻译： 提供具有低功耗的半导体集成电路。 在一个实施例中，半导体集成电路包括连接在第一电源线和虚拟接地线之间的逻辑电路部分。 逻辑电路部分包括具有第一阈值电压的至少一个NMOS晶体管和具有第二阈值电压的至少一个PMOS晶体管。 半导体集成电路还包括连接在虚拟接地线和接地电压之间的第一MOS晶体管，其中第一MOS晶体管具有第一阈值电压，并将接地电压施加到虚拟接地线处于活动状态。 还包括在半导体集成电路中的控制器是连接到第一MOS晶体管的控制器，其中控制器将该接地电压施加到处于激活状态的第一MOS晶体管，并且将来自大容量电力线的批量电压施加在待机状态 以控制第一MOS晶体管的阈值电压。