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    Internal voltage generator circuit and semiconductor memory device using the same
    2.
    发明授权
    Internal voltage generator circuit and semiconductor memory device using the same 有权
    内部电压发生器电路和使用其的半导体存储器件

    公开(公告)号：US08416631B2

    公开(公告)日：2013-04-09

    申请号：US12874299

    申请日：2010-09-02

    申请人： Young-Hoon Kim ,  Nam-Jong Kim

    发明人： Young-Hoon Kim ,  Nam-Jong Kim

    IPC分类号： G11C5/14

    CPC分类号： G11C7/12 ,  G11C5/14

    摘要： An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and to output an internal voltage at an internal voltage output terminal, based on the comparison signal. The circuit further includes a voltage divider circuit including first and second resistor units and a first voltage output terminal between the first and second resistor units, configured to receive the internal voltage, and configured to output the first voltage based on the resistance values of the first and second resistor units, the first and second resistor units connected in series, and the first voltage being output through the first voltage output terminal. The circuit further includes a control signal generator circuit configured to generate at least one resistor control signal for controlling the resistance value of the first resistor unit and at least one resistor control signal for controlling the resistance value of the second resistor unit, on the basis of the comparison signal and a precharge command.

    摘要翻译： 公开了内部电压发生器电路。 内部电压发生器电路包括比较器，其被配置为将第一电压与参考电压进行比较并输出比较信号。 电路还包括内部电压驱动器，其被配置为接收外部电压和比较信号，并且基于比较信号输出内部电压输出端子处的内部电压。 该电路还包括一个分压器电路，包括第一和第二电阻器单元以及第一和第二电阻器单元之间的第一电压输出端子，其被配置为接收内部电压，并且被配置为基于第一和第二电阻器的电阻值输出第一电压 以及第二电阻器单元，第一和第二电阻器单元串联连接，第一电压通过第一电压输出端子输出。 该电路还包括一个控制信号发生器电路，该电路被配置为产生用于控制第一电阻器单元的电阻值的至少一个电阻控制信号和用于控制第二电阻器单元的电阻值的至少一个电阻控制信号 比较信号和预充电指令。

    Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature
    5.
    发明授权
    Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature 失效
    温度检测器使用单个分支提供多个检测温度点和检测移位温度的方法

    公开(公告)号：US07315792B2

    公开(公告)日：2008-01-01

    申请号：US11151448

    申请日：2005-06-14

    申请人： Young-sun Min ,  Nam-jong Kim

    发明人： Young-sun Min ,  Nam-jong Kim

    IPC分类号： G01F15/00

    CPC分类号： G11C29/028 ,  G11C7/04 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40626 ,  G11C29/02 ,  G11C29/50016 ,  G11C2029/5002

    摘要： A temperature detector and method of detecting a shifted temperature provides multiple detected temperature points using a single branch. The temperature detector generates multiple detected temperature points in response to temperature control signals sequentially generated in a single branch. Since a shifted temperature for the single branch is found and a trimming operation in response to the shifted temperature is carried out, the test time is reduced. Various refresh periods can be set in response to various trip point temperatures and thus power consumption of a DRAM can be decreased.

    摘要翻译： 温度检测器和检测转换温度的方法使用单个分支提供多个检测到的温度点。 温度检测器响应于在单个分支中顺序产生的温度控制信号而产生多个检测到的温度点。 由于发现单个分支的移位温度，并且执行响应于移位的温度的修整操作，所以测试时间减少。 可以响应于各种跳变点温度来设置各种刷新周期，因此可以降低DRAM的功耗。

    LEVEL SHIFTER WITH LOW LEAKAGE CURRENT
    6.
    发明申请
    LEVEL SHIFTER WITH LOW LEAKAGE CURRENT 失效
    低泄漏电流的液位变送器

    公开(公告)号：US20070236272A1

    公开(公告)日：2007-10-11

    申请号：US11764241

    申请日：2007-06-18

    申请人： Young-sun Min ,  Nam-Jong Kim

    发明人： Young-sun Min ,  Nam-Jong Kim

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113

    摘要： A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow Vcc and VOlow

    摘要翻译： 电压电平移位电路包括第一级，其接收具有电压电平Vcc和Vss的输入信号，其中Vcc> Vss，并且其输出互补的第一和第二中间信号，其中互补的第一和第二中间信号具有电压电平VI 高和VI 低，其中VI高低> VI 以及第二级，其接收所述第一和第二中间信号，并且输出互补的第一和第二输出信号，其中所述互补的第一和第二输出信号具有电压电平VO高电平和VO < / SUB>，其中VO VO 低，其中VI高的 低 Vcc和VO低

    MULTI-PORT SEMICONDUCTOR MEMORY DEVICE AND SIGNAL INPUT/OUTPUT METHOD THEREFOR
    7.
    发明申请
    MULTI-PORT SEMICONDUCTOR MEMORY DEVICE AND SIGNAL INPUT/OUTPUT METHOD THEREFOR 有权
    多端口半导体存储器件及其信号输入/输出方法

    公开(公告)号：US20070195633A1

    公开(公告)日：2007-08-23

    申请号：US11466415

    申请日：2006-08-22

    申请人： Hyo-Joo AHN ,  Nam-Jong KIM

    发明人： Hyo-Joo AHN ,  Nam-Jong KIM

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C7/1075 ,  G11C8/16 ,  G11C29/1201 ,  G11C29/48

    摘要： A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The different input/output ports include a first input/output port through which a first signal is input/output and a second input/output port through which a second signal different from the first signal is input/output. The memory region is divided into a plurality of memory regions. The invention provides effects of reducing the number of test pins and improving test efficiency.

    摘要翻译： 因此，提供了多端口半导体存储器件和信号输入/输出方法。 在一个实施例中，多端口半导体存储器件包括多个不同的输入/输出端口和存储器阵列。 存储器阵列具有通过使用不同的输入/输出端口访问的至少一个存储器区域。 不同的输入/输出端口包括输入/​​输出第一信号的第一输入/输出端口和与第一信号不同的第二信号被输入/输出的第二输入/输出端口。 存储区域被分成多个存储区域。 本发明提供减少测试针数量并提高测试效率的效果。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR 失效
    半导体存储器件及其方法

    公开(公告)号：US20070171755A1

    公开(公告)日：2007-07-26

    申请号：US11616846

    申请日：2006-12-27

    申请人： Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    发明人： Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/406 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618

    摘要： A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

    摘要翻译： 提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。 在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域 多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。 授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

    Anti-fuse circuit and anti-fusing method
    10.
    发明申请
    Anti-fuse circuit and anti-fusing method 失效
    防熔丝电路和防熔方法

    公开(公告)号：US20060268646A1

    公开(公告)日：2006-11-30

    申请号：US11443307

    申请日：2006-05-31

    申请人： Nam-Jong Kim ,  Young-Sun Min

    发明人： Nam-Jong Kim ,  Young-Sun Min

    IPC分类号： G11C17/18

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： An anti-fuse and an anti-fusing method are disclosed. An example embodiment of the present invention is directed to an anti-fuse circuit, including an anti-fuse receiving a first voltage, a pull-up transistor coupled between the anti-fuse and a first node, the pull-up transistor configured to pull up a voltage at the first node to the first voltage when the anti-fuse is in a given operation mode, a pull-down transistor configured to pull down the voltage at the first node to a second voltage in response to a pull-down control signal, the second voltage lower than the first voltage, a voltage level detector configured to compare a detection reference voltage level with a voltage level at the first node to generate a detection output signal and a pull-down control circuit configured to generate the pull-down control signal based on a fuse input signal and the detection output signal.

    摘要翻译： 公开了一种抗熔丝和抗融合方法。 本发明的示例性实施例涉及一种抗熔丝电路，其包括接收第一电压的反熔丝，耦合在反熔丝和第一节点之间的上拉晶体管，所述上拉晶体管被配置为拉 当所述反熔丝处于给定的操作模式时，将所述第一节点处的电压升高到所述第一电压，配置为响应于下拉控制将所述第一节点处的电压下拉到第二电压的下拉晶体管 信号，所述第二电压低于所述第一电压;电压电平检测器，被配置为将检测参考电压电平与所述第一节点处的电压电平进行比较，以产生检测输出信号;以及下拉控制电路， 基于保险丝输入信号和检测输出信号的下降控制信号。