公开(公告)号：US06950329B2

公开(公告)日：2005-09-27

申请号：US10871623

申请日：2004-06-18

申请人： Masahiro Tanaka ,  Toshiyuki Nishihara ,  Yukihisa Tsuneda

发明人： Masahiro Tanaka ,  Toshiyuki Nishihara ,  Yukihisa Tsuneda

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H03M1/74

CPC分类号： G11C11/22

摘要： A D/A converter capable of temporally controlling output of analog data during D/A conversion is provided. The digital to analog converter includes a ferroelectric non-volatile semiconductor memory. The ferroelectric non-volatile semiconductor memory includes a data line, a memory unit which has M memory cells, and M plate lines. Each of the memory cells includes a first electrode, a ferroelectric layer and a second electrode. The first electrode of the memory cells is shared in the memory unit and is connected to the data line. The second electrode of the mth memory cell is connected to the mth plate line. And the area of the ferroelectric layer of the memory cells varies among the memory cells.

摘要翻译： 提供了能够在D / A转换期间暂时控制模拟数据输出的D / A转换器。 数模转换器包括铁电非易失性半导体存储器。 铁电非易失性半导体存储器包括数据线，具有M个存储单元的存储单元和M板线。 每个存储单元包括第一电极，铁电层和第二电极。 存储器单元的第一电极在存储器单元中共享并连接到数据线。 第m个存储单元的第二电极连接到第m个板线。 并且存储单元的铁电层的面积在存储单元之间变化。

公开(公告)号：US09202830B2

公开(公告)日：2015-12-01

申请号：US12926345

申请日：2010-11-12

申请人： Toshiyuki Nishihara ,  Hirofumi Sumi

发明人： Toshiyuki Nishihara ,  Hirofumi Sumi

IPC分类号： H04N3/14 ,  H04N5/335 ,  H01L27/146

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14689

摘要： An imaging element includes an amplifying transistor. A signal charge from the photodiode is transferable to the gate of amplifying transistor, the photodiode being within a semiconductor substrate. The source and drain of the amplifying transistor are electrically isolated from a semiconductor substrate, wherein the source is within a well or the source and drain are within a silicon-on-insulator layer.

摘要翻译： 成像元件包括放大晶体管。 来自光电二极管的信号电荷可转移到放大晶体管的栅极，光电二极管位于半导体衬底内。 放大晶体管的源极和漏极与半导体衬底电隔离，其中源极在阱内，或源极和漏极位于绝缘体上硅层内。

公开(公告)号：US09183132B2

公开(公告)日：2015-11-10

申请号：US11493904

申请日：2006-07-27

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： A storage device enabling realization of a new storage configuration enabling apparent elimination of the overhead and enabling high speed access all the time particularly when constructing a high parallel configured high speed flash memory system, that is, a storage device having a flash memory as a main storage and having the function of rewriting at least a partial region of the flash memory by additional writing update data in an empty region and invalidating original data and, at the time of standby of the device where there is no access from the outside, performing processing for automatically restoring the invalidated region to an empty region, and a computer system and a storage system using the same.

摘要翻译： 一种存储装置，其能够实现新的存储配置，从而明显地消除开销并且始终实现高速访问，特别是在构建高并行配置的高速闪速存储器系统时，即具有闪速存储器作为主要的存储装置 存储并且具有通过在空白区域中附加写入更新数据来重新写入闪速存储器的至少部分区域的功能，并且使原始数据无效，并且在不存在来自外部的设备的待机时，执行处理 用于将无效区域自动恢复到空白区域，以及使用该区域的计算机系统和存储系统。

公开(公告)号：US20120081589A1

公开(公告)日：2012-04-05

申请号：US13241758

申请日：2011-09-23

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： H04N5/335 ,  H01L27/146

CPC分类号： H04N5/37455 ,  G01J1/44 ,  G01J2001/444 ,  H04N5/32 ,  H04N5/3355 ,  H04N5/3535 ,  H04N5/355 ,  H04N5/357 ,  H04N5/363 ,  H04N5/3742 ,  H04N5/378

摘要： An imaging device includes: a pixel array section functioning as a light receiving section which includes photoelectric conversion devices and in which a plurality of pixels, which output electric signals when photons are incident, are disposed in an array; a sensing circuit section in which a plurality of sensing circuits, which receive the electric signals from the pixels and perform binary determination regarding whether or not there is an incidence of photons on the pixels in a predetermined period, are arrayed; and a determination result integration circuit section having a function of integrating a plurality of determination results of the sensing circuits for the respective pixels or for each pixel group, wherein the determination result integration circuit section derives the amount of photon incidence on the light receiving section by performing photon counting for integrating the plurality of determination results in the plurality of pixels.

摘要翻译： 成像装置包括：作为包含光电转换装置的光接收部的像素阵列部，其中在光子入射时输出电信号的多个像素排列成阵列; 感测电路部分，其中接收来自像素的电信号并且执行关于在预定周期中是否存在像素的光子入射的二进制确定的多个感测电路被排列; 以及确定结果积分电路部分，其具有对各像素或每个像素组的感测电路的多个确定结果进行积分的功能，其中确定结果积分电路部分通过以下方式导出光接收部分上的光子入射量 执行用于将所述多个确定结果集成在所述多个像素中的光子计数。

公开(公告)号：US20110205416A1

公开(公告)日：2011-08-25

申请号：US13126790

申请日：2009-11-25

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： H04N5/335

CPC分类号： H04N5/3745 ,  H01L27/14609 ,  H04N5/3559

摘要： A pixel circuit has first, second, and third field effect transistors integrated and connected in series from a photoelectric conversion element to a side of an amplifier circuit. The first and second field effect transistors have gate electrodes to be simultaneously collectively driven. A threshold voltage of the first field effect transistor is set to be higher than that of the second field effect transistor. As the gate electrodes are driven step by step, electrons generated by the photoelectric conversion element and transferred via the first field effect transistor are accumulated in a channel region of the second field effect transistor. The electrons accumulated in the channel region are transferred to an input of the amplifier circuit via the third field effect transistor.

摘要翻译： 像素电路具有从光电转换元件串联连接到放大器电路侧的第一，第二和第三场效应晶体管。 第一和第二场效应晶体管具有同时共同驱动的栅电极。 第一场效应晶体管的阈值电压被设定为高于第二场效应晶体管的阈值电压。 随着门电极逐步驱动，由光电转换元件产生并通过第一场效应晶体管传送的电子被累积在第二场效应晶体管的沟道区中。 积累在沟道区中的电子经由第三场效应晶体管传送到放大器电路的输入端。

公开(公告)号：US20110134264A1

公开(公告)日：2011-06-09

申请号：US12926345

申请日：2010-11-12

申请人： Toshiyuki Nishihara ,  Hirofumi Sumi

发明人： Toshiyuki Nishihara ,  Hirofumi Sumi

IPC分类号： H04N5/228 ,  H04N5/335

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14689

摘要： An imaging element includes an amplifying transistor. A signal charge from the photodiode is transferable to the gate of amplifying transistor, the photodiode being within a semiconductor substrate. The source and drain of the amplifying transistor are electrically isolated from a semiconductor substrate, wherein the source is within a well or the source and drain are within a silicon-on-insulator layer.

摘要翻译： 成像元件包括放大晶体管。 来自光电二极管的信号电荷可转移到放大晶体管的栅极，光电二极管位于半导体衬底内。 放大晶体管的源极和漏极与半导体衬底电隔离，其中源极在阱内，或源极和漏极位于绝缘体上硅层内。

公开(公告)号：USD582320S1

公开(公告)日：2008-12-09

申请号：US29304671

申请日：2008-03-05

申请人： Shunji Tanaka ,  Toshiyuki Nishihara

设计人： Shunji Tanaka ,  Toshiyuki Nishihara

公开(公告)号：US07193923B2

公开(公告)日：2007-03-20

申请号：US11201309

申请日：2005-08-11

申请人： Toshiyuki Nishihara ,  Hidetoshi Yamanaka ,  Daisuke Yoshioka

发明人： Toshiyuki Nishihara ,  Hidetoshi Yamanaka ,  Daisuke Yoshioka

IPC分类号： G11C8/00

CPC分类号： G06F12/0802 ,  G06F12/0246

摘要： A semiconductor memory device using inexpensive block access semiconductor memories for storage media and able to be treated like a usual randomly accessible system memory, including a first semiconductor memory and a second semiconductor memory, wherein the second semiconductor memory is a cache of the first semiconductor memory, the first semiconductor memory is accessed via the second semiconductor memory, there are a first address region and a second address region on logical memory addresses accessed from the outside, at least part of the second semiconductor memory is mapped to the first address region, and a function of controlling data transfer between the first semiconductor memory and the second semiconductor memory by accessing the second address region is provided, and an access method and a memory control system of the same.

摘要翻译： 一种半导体存储器件，其使用用于存储介质的廉价块存取半导体存储器，并能够像通常的可随机存取的系统存储器那样被处理，包括第一半导体存储器和第二半导体存储器，其中第二半导体存储器是第一半导体存储器 通过第二半导体存储器访问第一半导体存储器，在从外部访问的逻辑存储器地址上存在第一地址区域和第二地址区域，第二半导体存储器的至少一部分被映射到第一地址区域，以及 提供了通过访问第二地址区域来控制第一半导体存储器和第二半导体存储器之间的数据传送的功能，以及其访问方法和存储器控制系统。

公开(公告)号：US20060114710A1

公开(公告)日：2006-06-01

申请号：US11324658

申请日：2006-01-03

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G11C11/22

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential is provided to the bit line connected to the one of said memory cells, and a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.

公开(公告)号：US20060109703A1

公开(公告)日：2006-05-25

申请号：US11324610

申请日：2006-01-03

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G11C11/22

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential is provided to the bit line connected to the one of said memory cells, and a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.