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    Semiconductor memory device and access method and memory control system for same
    1.
    发明授权
    Semiconductor memory device and access method and memory control system for same 有权
    半导体存储器件及其存取方法和存储器控制系统相同

    公开(公告)号：US07193923B2

    公开(公告)日：2007-03-20

    申请号：US11201309

    申请日：2005-08-11

    申请人： Toshiyuki Nishihara ,  Hidetoshi Yamanaka ,  Daisuke Yoshioka

    发明人： Toshiyuki Nishihara ,  Hidetoshi Yamanaka ,  Daisuke Yoshioka

    IPC分类号： G11C8/00

    CPC分类号： G06F12/0802 ,  G06F12/0246

    摘要： A semiconductor memory device using inexpensive block access semiconductor memories for storage media and able to be treated like a usual randomly accessible system memory, including a first semiconductor memory and a second semiconductor memory, wherein the second semiconductor memory is a cache of the first semiconductor memory, the first semiconductor memory is accessed via the second semiconductor memory, there are a first address region and a second address region on logical memory addresses accessed from the outside, at least part of the second semiconductor memory is mapped to the first address region, and a function of controlling data transfer between the first semiconductor memory and the second semiconductor memory by accessing the second address region is provided, and an access method and a memory control system of the same.

    摘要翻译： 一种半导体存储器件，其使用用于存储介质的廉价块存取半导体存储器，并能够像通常的可随机存取的系统存储器那样被处理，包括第一半导体存储器和第二半导体存储器，其中第二半导体存储器是第一半导体存储器 通过第二半导体存储器访问第一半导体存储器，在从外部访问的逻辑存储器地址上存在第一地址区域和第二地址区域，第二半导体存储器的至少一部分被映射到第一地址区域，以及 提供了通过访问第二地址区域来控制第一半导体存储器和第二半导体存储器之间的数据传送的功能，以及其访问方法和存储器控制系统。

    Semiconductor memory device and access method and memory control system for same
    2.
    发明申请
    Semiconductor memory device and access method and memory control system for same 有权
    半导体存储器件及其存取方法和存储器控制系统相同

    公开(公告)号：US20060047888A1

    公开(公告)日：2006-03-02

    申请号：US11201309

    申请日：2005-08-11

    申请人： Toshiyuki Nishihara ,  Hidetoshi Yamanaka ,  Daisuke Yoshioka

    发明人： Toshiyuki Nishihara ,  Hidetoshi Yamanaka ,  Daisuke Yoshioka

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0802 ,  G06F12/0246

    摘要： A semiconductor memory device using inexpensive block access semiconductor memories for storage media and able to be treated like a usual randomly accessible system memory, including a first semiconductor memory and a second semiconductor memory, wherein the second semiconductor memory is a cache of the first semiconductor memory, the first semiconductor memory is accessed via the second semiconductor memory, there are a first address region and a second address region on logical memory addresses accessed from the outside, at least part of the second semiconductor memory is mapped to the first address region, and a function of controlling data transfer between the first semiconductor memory and the second semiconductor memory by accessing the second address region is provided, and an access method and a memory control system of the same.

    摘要翻译： 一种半导体存储器件，其使用用于存储介质的廉价块存取半导体存储器，并能够像通常的可随机存取的系统存储器那样被处理，包括第一半导体存储器和第二半导体存储器，其中第二半导体存储器是第一半导体存储器 通过第二半导体存储器访问第一半导体存储器，在从外部访问的逻辑存储器地址上存在第一地址区域和第二地址区域，第二半导体存储器的至少一部分映射到第一地址区域，以及 提供了通过访问第二地址区域来控制第一半导体存储器和第二半导体存储器之间的数据传送的功能，以及其访问方法和存储器控制系统。

    Semiconductor memory device and signal processing system
    3.
    发明申请
    Semiconductor memory device and signal processing system 失效
    半导体存储器件和信号处理系统

    公开(公告)号：US20050259479A1

    公开(公告)日：2005-11-24

    申请号：US11126302

    申请日：2005-05-11

    申请人： Hidetoshi Yamanaka ,  Toshiyuki Nishihara ,  Shigeru Atsumi ,  Daisuke Yoshioka

    发明人： Hidetoshi Yamanaka ,  Toshiyuki Nishihara ,  Shigeru Atsumi ,  Daisuke Yoshioka

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C11/18 ,  G11C16/04 ,  G11C16/26 ,  G11C5/00

    CPC分类号： G11C7/1039 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C8/06 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/107

    摘要： A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.

    摘要翻译： 一种半导体存储装置，其能够连续地高速读出数据，与多个存储体相对应地设置有用于保存用于读取单元阵列的数据的地址的当前地址寄存器，能够提前接收并保持预留地址的预留地址寄存器 以及用于使当前地址寄存器保持在保留地址寄存器中的保留地址的存储体控制电路，使数据被读出，使数据锁存电路在数据从 通过保存在当前地址中并保存在数据锁存电路中的存储在存储器中的存储体的单元阵列变得能够被传送到外部，以及与其相关的信号处理系统。

    Semiconductor memory device and signal processing system
    4.
    发明授权
    Semiconductor memory device and signal processing system 失效
    半导体存储器件和信号处理系统

    公开(公告)号：US07283405B2

    公开(公告)日：2007-10-16

    申请号：US11126302

    申请日：2005-05-11

    申请人： Hidetoshi Yamanaka ,  Toshiyuki Nishimura ,  Shigeru Atsumi ,  Daisuke Yoshioka

    发明人： Hidetoshi Yamanaka ,  Toshiyuki Nishimura ,  Shigeru Atsumi ,  Daisuke Yoshioka

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C11/4093

    CPC分类号： G11C7/1039 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C8/06 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/107

    摘要： A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.

    摘要翻译： 一种半导体存储装置，其能够连续地高速读出数据，与多个存储体相对应地设置有用于保存用于读取单元阵列的数据的地址的当前地址寄存器，能够提前接收并保持预留地址的预留地址寄存器 以及用于使当前地址寄存器保持在保留地址寄存器中的保留地址的存储体控制电路，使数据被读出，使数据锁存电路在数据从 通过保存在当前地址中并保存在数据锁存电路中的存储在存储器中的存储体的单元阵列变得能够被传送到外部，以及与其相关的信号处理系统。

    Semiconductor nonvolatile memory device and method of producing the same
    8.
    发明授权
    Semiconductor nonvolatile memory device and method of producing the same 有权
    半导体非易失性存储器件及其制造方法，包括在隔离绝缘膜上形成浮栅的部分

    公开(公告)号：US06403421B1

    公开(公告)日：2002-06-11

    申请号：US09583906

    申请日：2000-05-31

    申请人： Naoshi Ikeda ,  Ikuhiro Yamamura ,  Hidetoshi Yamanaka

    发明人： Naoshi Ikeda ,  Ikuhiro Yamamura ,  Hidetoshi Yamanaka

    IPC分类号： H01L21336

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A semiconductor nonvolatile memory device using SA-STI cells improved in quality and suitable for increasing the degree of integration is provided with a semiconductor substrate having in its surface a channel formation region; an element isolation insulating film buried in a trench formed in the semiconductor substrate so as to divide the channel formation region into a plurality of regions; a gate insulating film formed on the channel formation region; a floating gate provided with a first floating gate formed at an upper layer of the gate insulating film and second floating gates formed at facing sides of the same; an inter-layer insulating film formed at an upper layer of the first floating gate and the second floating gates; a control gate formed at an upper layer of the inter-layer insulating film; and a source-drain region former connected to the channel formation region.

    摘要翻译： 使用在其表面具有沟道形成区域的半导体衬底设置使用质量提高并适于增加集成度的SA-STI单元的半导体非易失性存储器件; 掩模在半导体衬底中形成的沟槽中的元件隔离绝缘膜，以便将沟道形成区域分成多个区域; 形成在沟道形成区上的栅极绝缘膜; 设置有形成在栅绝缘膜的上层的第一浮栅和形成在其相对侧的第二浮栅的浮置栅; 形成在第一浮动栅极和第二浮动栅极的上层的层间绝缘膜; 形成在所述层间绝缘膜的上层的控制栅极; 以及连接到沟道形成区的源极 - 漏极区前体。