Abstract:
A level shifter has a pair of P-type MOS transistor switches, a pair of N-type MOS transistor switches, an inverter and a plurality of triggers. The triggers are connected to gates of high-voltage devices (N-type MOS transistor switches) and substrates of the high-voltage devices, so that the triggers can produce a trigger signal for a period of time after receiving a low voltage control signal in order to change voltages on the substrates at transition and further reduce threshold voltages of the substrates to increase transition speed of the shifter circuit.
Abstract:
An LCD panel driving method and device with charge sharing is disclosed. The LCD panel includes a plurality of switches, a plurality of data lines, a signal driving circuit for generating a plurality of image signals, a charge sharing common voltage driving circuit and a common capacitor having one end connected to the charge sharing common voltage driving circuit through a common voltage node. The method turns the switches on to thereby form the charge sharing common voltage driving circuit and the signal driving circuit as a short circuit, such that charges stored in the common capacitor flow into the data lines to drive the common voltage node to enter in an inverse phase state in order to sequentially turn the switches on and then off to accordingly sample the respective data lines.
Abstract:
A defect detection method is disclosed, in which the method includes: providing a semiconductor sample, wherein the semiconductor sample comprises at least one defect; utilizing a failure analysis for detecting at least one suspected area on the backside of the semiconductor sample; utilizing a physical energy for forming a plurality of reference marks around the suspected area on the backside of the semiconductor sample; and utilizing the reference marks for determining the relative location of the defect on the front side of the semiconductor sample.
Abstract:
A digital signal processor (DSP) circuit is configured to recursively retrieve and process pairs of data points in a symmetric digital filter. The data points are retrieved from an external source (e.g., compact disk) at a first frequency, and processed within the DSP at a second frequency. The DSP employs a floating pointer scheme, which effectively functions a buffer to thereby compensate for jitter or drift between the first and second frequencies.
Abstract:
A digital-to-analog converter (DAC) for generating a pulse width modulated (PWM) signal. A dual-DAC implementation includes a read-only memory (ROM) containing a plurality of addressable output signals, respective shift left and shift right registers configured to simultaneously receive an output signal from the ROM, and respective first and second DACs are configured to receive the left shifted output and right shifted output, respectively, from the shift left and shift right registers. Both DAC outputs are applied to an analog summer which generates an output signal indicative of the sum of the outputs from the two DACs.