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公开(公告)号：US20240137010A1
公开(公告)日：2024-04-25
申请号：US18482983
申请日：2023-10-09
申请人： Aktiebolaget SKF
发明人： James P. LEBLANC , Patrik PÄÄJÄRVI
CPC分类号： H03H17/0628 , H03H17/0213
摘要： A device for processing a digital signal includes a Farrow structure (14) that applies to the digital signal a time-varying sample rate conversion from the fixed sample rate to a time varying sampling. The digital signal sampled at the time varying sampling is a resulting signal. The Farrow structure (14) is controlled from a control variable. A spectral analysis means (15) performs a spectral analysis of the resulting signal to determine the frequency values of the resulting signal. A determining means (16) determines a sparseness parameter of the frequency values of the resulting signal. A controlling means (17) modifies the control variable according to the value of the sparseness parameter.
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公开(公告)号：US09973172B2
公开(公告)日：2018-05-15
申请号：US15800855
申请日：2017-11-01
摘要： Provided, among other things, is an apparatus for digitally processing a discrete-time signal that includes: an input line for accepting an input signal, processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. First and second lowpass filters, each having a frequency response with a magnitude that varies approximately with frequency according to a product of raised functions, are included within baseband processors in such processing branches.
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公开(公告)号：US09837990B1
公开(公告)日：2017-12-05
申请号：US15366384
申请日：2016-12-01
摘要： Provided, among other things, is an apparatus for digitally processing a discrete-time signal that includes: an input line for accepting an input signal, processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. First and second lowpass filters, each having a frequency response with a magnitude that varies approximately with frequency according to a product of raised functions, are included within baseband processors in such processing branches.
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公开(公告)号：US20150341159A1
公开(公告)日：2015-11-26
申请号：US14817996
申请日：2015-08-04
CPC分类号： H04L7/0008 , H03H17/0614 , H03H17/0628 , H03H2218/04 , H04L7/0025 , H04L7/005 , H04L7/02
摘要： An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
摘要翻译： 内插器或抽取器包括在第一和第二时钟域之间的信号路径中的弹性存储元件。 弹性元件可以例如是有利地允许采样时钟的短期变化被吸收的FIFO。 反馈机制控制基于Δ-Σ调制的模N计数器的采样时钟发生器。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。
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公开(公告)号：US09130700B2
公开(公告)日：2015-09-08
申请号：US14295233
申请日：2014-06-03
CPC分类号： H04L7/0008 , H03H17/0614 , H03H17/0628 , H03H2218/04 , H04L7/0025 , H04L7/005 , H04L7/02
摘要： Interpolator and decimator apparatuses and methods are improved by the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
摘要翻译： 通过在信号路径中添加弹性存储元件来改进插值器和抽取器装置和方法。 在一个示例性实施例中，弹性元件包括有利地允许采样时钟的短期变化被吸收的FIFO，并且还提供用于控制基于Δ-Σ调制的模N计数器的采样时钟发生器的反馈机制。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。
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公开(公告)号：US09052991B2
公开(公告)日：2015-06-09
申请号：US13686895
申请日：2012-11-27
发明人： Boaz Castro
CPC分类号： G06F17/00 , H03H17/0628
摘要： A method for audio sample rate conversion may include receiving an audio signal at a first rate, the audio signal having a fundamental frequency, determining absolute derivatives of the audio signal at the first rate, and generating a weighted sum of the absolute derivatives to arrive at a combined absolute derivative. The combined absolute derivative may be analyzed to locate a local minimum of the combined absolute derivative, a location in the audio signal may be selected based on the local minimum of the combined absolute derivative and at least one audio sample in the audio signal may be altered at the selected location to develop an audio signal at a second rate.
摘要翻译： 用于音频采样率转换的方法可以包括以第一速率接收音频信号，音频信号具有基频，以第一速率确定音频信号的绝对导数，并产生绝对导数的加权和以得到 一个绝对衍生的组合。 可以分析组合的绝对导数以定位组合绝对导数的局部最小值，可以基于组合绝对导数的局部最小值来选择音频信号中的位置，并且音频信号中的至少一个音频采样可以被改变 在所选择的位置以以第二速率开发音频信号。
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公开(公告)号：US09000958B1
公开(公告)日：2015-04-07
申请号：US14206522
申请日：2014-03-12
发明人： Mi Jeong Park , Ik Soo Eo , Sang-Kyun Kim
IPC分类号： H03M7/00
CPC分类号： H03H17/0628
摘要： A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.
摘要翻译： 数据速率转换装置产生表示要采样的存储器地址位置的第一参数和表示估计时间点的相位值的第二参数，基于输入时钟将输入数据记录在存储器中，使用 基于输出时钟的第一参数，并且使用连续数据，多个滤波器系数和第二参数来生成和输出最终数据。
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公开(公告)号：US20140148932A1
公开(公告)日：2014-05-29
申请号：US13686895
申请日：2012-11-27
发明人： Boaz CASTRO
IPC分类号： G06F17/00
CPC分类号： G06F17/00 , H03H17/0628
摘要： A method for audio sample rate conversion may include receiving an audio signal at a first rate, the audio signal having a fundamental frequency, determining absolute derivatives of the audio signal at the first rate, and generating a weighted sum of the absolute derivatives to arrive at a combined absolute derivative. The combined absolute derivative may be analyzed to locate a local minimum of the combined absolute derivative, a location in the audio signal may be selected based on the local minimum of the combined absolute derivative and at least one audio sample in the audio signal may be altered at the selected location to develop an audio signal at a second rate.
摘要翻译： 用于音频采样率转换的方法可以包括以第一速率接收音频信号，音频信号具有基频，以第一速率确定音频信号的绝对导数，并产生绝对导数的加权和以得到 一个绝对衍生的组合。 可以分析组合绝对导数以定位组合绝对导数的局部最小值，可以基于组合绝对导数的局部最小值来选择音频信号中的位置，并且音频信号中的至少一个音频采样可以被改变 在所选择的位置以以第二速率开发音频信号。
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公开(公告)号：US08494104B2
公开(公告)日：2013-07-23
申请号：US13236291
申请日：2011-09-19
CPC分类号： G10L19/00 , H03H17/0422 , H03H17/0628 , H04L7/0008 , H04L7/0025 , H04L7/0029
摘要： A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions.
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公开(公告)号：US20120033771A1
公开(公告)日：2012-02-09
申请号：US12850162
申请日：2010-08-04
申请人： Jeff Wei
发明人： Jeff Wei
IPC分类号： H04L7/00
CPC分类号： H04J3/0685 , H03H17/0275 , H03H17/0628 , H03H2218/06 , H04J3/04 , H04L25/068
摘要： A method of sample rate conversion and clock synchronization for multiple asynchronous input signals using a single processing core. A sample processing clock with a frequency equal to or higher than the input signal clock frequencies is provided. The clock period is divided into a number of time slots corresponding to the input signals. For each valid sample of an input signal, the core performs a first stage processing operation on the sample. Subsequently, for each required sample of an output signal, the core performs a second stage processing operation to generate the output sample.
摘要翻译： 使用单个处理核心的多个异步输入信号的采样率转换和时钟同步的方法。 提供频率等于或高于输入信号时钟频率的采样处理时钟。 时钟周期被分成对应于输入信号的多个时隙。 对于输入信号的每个有效样本，核对样本执行第一阶段处理操作。 随后，对于输出信号的每个所需样本，核进行第二阶段处理操作以产生输出样本。
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