Phase locked loop circuit
    11.
    发明授权
    Phase locked loop circuit 失效
    锁相环电路

    公开(公告)号:US5334954A

    公开(公告)日:1994-08-02

    申请号:US980946

    申请日:1992-11-25

    CPC classification number: H03L7/107 H03L7/191 H03L7/0898 H03L7/095

    Abstract: A phase control circuit for controlling the relative phase of periodic components of two logic signals having the same frequency, and one of which periodic components has a pulse-duty factor different from 50:50, said circuit includes a signal source which provides a control signal for regulating the relative phase of the periodic components of said logic signals. The control signal has a first value for phase relationships in a predetermined range of values and a second value for phase relationships outside said range of values. A phase lock detector detects the lock status of the periodic components of the logic signals. Another signal source provides a third logic signal having a periodic component having the same frequency as the periodic component of each of the two logic signals and a pulse width substantially wider than that of the two logic signals. A switch is actuated by the phase lock detector and applies the third logic signal to the signal source when the two logic signals are out-of-lock whereby the control signal has the first value when the two logic signals are phase locked and the second value when the two logic signal are not phase locked.

    Abstract translation: 一种相位控制电路,用于控制具有相同频率的两个逻辑信号的周期分量的相对相位,并且其中一个周期分量具有不同于50:50的脉冲占空因数,所述电路包括提供控制信号的信号源 用于调节所述逻辑信号的周期性分量的相对相位。 控制信号具有在预定值范围内的相位关系的第一值和在所述值范围之外的相位关系的第二值。 锁相检测器检测逻辑信号的周期性分量的锁定状态。 另一信号源提供具有周期分量的第三逻辑信号,该周期分量具有与两个逻辑信号中的每一个的周期分量相同的频率,以及比两个逻辑信号的脉冲宽度更宽的脉冲宽度。 一个开关由相位锁定检测器启动,并且当两个逻辑信号不合锁时,将第三逻辑信号施加到信号源,当两个逻辑信号被锁相时控制信号具有第一个值,而第二个值 当两个逻辑信号没有锁相时。

    Circuit arrangement for detecting a TV synchronizing signal
    12.
    发明授权
    Circuit arrangement for detecting a TV synchronizing signal 失效
    用于检测TV同步信号的电路装置

    公开(公告)号:US5274448A

    公开(公告)日:1993-12-28

    申请号:US908715

    申请日:1992-07-09

    CPC classification number: H04N5/12

    Abstract: A circuit for detecting a square wave television signal in a television receiver includes an oscillator for generating the square wave signal and a phase locked loop (PLL) for synchronizing the square wave signal with the syn pulses of the televsion receiver. The circuit also includes an integrator for switching the output signal of the PLL to a frequency stable square wave signal when the syn pulses are absent and a Schmitt trigger for closing the PPL when a threshold value is reached. With the invention, the syn signals are sensed and a first switchable constant current source increases the output voltage of the integrator for a predetermined period of time when syn pulses are present during the first half of the square wave signal and discharges the integrator when syn signals are absent from the second half of the square wave signal.

    Abstract translation: 用于检测电视接收机中的方波电视信号的电路包括用于产生方波信号的振荡器和用于使方波信号与电视接收机的同步脉冲同步的锁相环(PLL)。 该电路还包括一个积分器,用于在不存在同步脉冲时将PLL的输出信号切换到频率稳定的方波信号,以及当达到阈值时关闭PPL的施密特触发器。 利用本发明,感测同步信号,并且当方波信号的前半部分存在同步脉冲时,第一可切换恒定电流源将积分器的输出电压增加预定时间段,并且当顺序信号 不在方波信号的后半部分。

    Comparator circuit for an integrator
    13.
    发明授权
    Comparator circuit for an integrator 失效
    一个整合器的比较器电路

    公开(公告)号:US5237222A

    公开(公告)日:1993-08-17

    申请号:US707481

    申请日:1991-05-30

    CPC classification number: H03K5/2409

    Abstract: A comparator circuit for an integrator comprises first and second transistors triggered by the integrator. The integrator has a current-controlled input. The transistors generate respective comparator output control signals which change when the transistors switch between saturated and unsaturated states. The first and second transistors are complementary transistors. A first current source, comprising a third transistor, is coupled to a source of supply voltage. One of the first and second transistors forms a corresponding mirrored current source with respect to the first current source. The integrator comprises an integration capacitor coupled to the mirrored current source. An output stage is responsive to the output control signals from the first and second transistors.

    Abstract translation: 用于积分器的比较器电路包括由积分器触发的第一和第二晶体管。 积分器具有电流控制输入。 晶体管产生各自的比较器输出控制信号,当晶体管在饱和状态和不饱和状态之间切换时,其变化。 第一和第二晶体管是互补晶体管。 包括第三晶体管的第一电流源耦合到电源电压源。 第一和第二晶体管之一相对于第一电流源形成相应的镜像电流源。 积分器包括耦合到镜像电流源的积分电容器。 输出级响应于来自第一和第二晶体管的输出控制信号。

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