公开(公告)号：US06806530B2

公开(公告)日：2004-10-19

申请号：US10613412

申请日：2003-07-03

Applicant: Kwang-Tae Kim

Inventor： Kwang-Tae Kim

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: An EEPROM device and a method of fabricating same. In one aspect, an EEPROM device comprises: a memory transistor including a tunnel insulating layer, first conductive layer patterns, and second conductive layer patterns stacked on a first portion of a semiconductor substrate, and common source regions and floating junction regions arranged at opposite sides of the second conductive layer patterns; and a selection transistor, which is connected to the floating junction regions, and includes a gate insulating layer, the first conductive layer patterns, and the second conductive layer patterns stacked on a second portion of the semiconductor substrate, and drain regions arranged at one side of the second conductive layer patterns opposite the floating junction regions. The first conductive layer patterns in the memory transistor are separated by cell unit and floated, and the insulating layer and the second conductive layer patterns stacked on the first conductive layer patterns are connected to a cell and an adjacent cell, and the first conductive layer patterns and the second conductive layer patterns of the selection transistor are etched and connected by metal plugs. The EEPROM is fabricated using a simplified process which combines a floating gate mask and ion implantation mask into one mask, and which provides reduced resistance by connecting word lines using the metal plugs.

Abstract translation: 一种EEPROM器件及其制造方法。 一方面，一种EEPROM器件包括：存储晶体管，其包括隧道绝缘层，第一导电层图案和层叠在半导体衬底的第一部分上的第二导电层图案，以及布置在相对侧的公共源极区域和浮置接合区域 的第二导电层图案; 以及选择晶体管，其连接到浮置结区域，并且包括栅极绝缘层，第一导电层图案和层叠在半导体衬底的第二部分上的第二导电层图案，以及排列在一侧的漏极区域 的第二导电层图案与浮动结区域相对。 存储晶体管中的第一导电层图案由单元单元分离并浮置，并且堆叠在第一导电层图案上的绝缘层和第二导电层图案连接到单元和相邻单元，并且第一导电层图案 并且选择晶体管的第二导电层图案被金属插塞蚀刻和连接。 使用将浮栅掩模和离子注入掩模组合成一个掩模的简化工艺制造EEPROM，并且通过使用金属插头连接字线来提供降低的电阻。

公开(公告)号：USD610879S1

公开(公告)日：2010-03-02

申请号：US29337811

申请日：2009-05-29

Applicant: Kwang-Tae Kim

Designer： Kwang-Tae Kim

公开(公告)号：US20080197401A1

公开(公告)日：2008-08-21

申请号：US12026812

申请日：2008-02-06

Applicant: Eun-Mi Hong ,  Kwang-Tae Kim ,  Ji-Hoon Park

Inventor： Eun-Mi Hong ,  Kwang-Tae Kim ,  Ji-Hoon Park

IPC: H01L27/105 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract translation: 提供一种制造非易失性存储器件的方法。 该方法包括在限定活性区域的半导体衬底中形成隔离层并在隔离层上形成模制图案。 第一导电层形成在模制图案的侧壁和顶表面上以及半导体衬底上。 选择性地去除模制图案的顶表面上的第一导电层，形成导电图案。 导电图案包括设置在有源区域上的主体板和从主体板的边缘延伸到模制图案的侧壁上的突起。 然后移除模制图案。 在隔离层和导电图案上形成栅极间电介质层。 还提供了使用该方法制造的非易失性存储器件。

公开(公告)号：US20060008985A1

公开(公告)日：2006-01-12

申请号：US11171706

申请日：2005-06-30

Applicant: Weon-Ho Park ,  Tea-Kwang Yu ,  Kyoung-Hwan Kim ,  Kwang-Tae Kim

Inventor： Weon-Ho Park ,  Tea-Kwang Yu ,  Kyoung-Hwan Kim ,  Kwang-Tae Kim

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  G11C16/0433 ,  H01L27/11524

Abstract: A method of forming a tunneling insulating layer having a size smaller than the size obtained by the resolution of a photolithography process is provided. The method includes the steps of forming a first insulating layer and a second insulating layer on a substrate, forming a re-flowable material layer pattern to re-flow the re-flowable material layer pattern, removing the second insulating layer and the first insulating layer to expose the substrate, and forming a tunneling insulating layer.

Abstract translation: 提供一种形成尺寸小于通过光刻工艺的分辨率获得的尺寸的隧道绝缘层的方法。 该方法包括在基板上形成第一绝缘层和第二绝缘层的步骤，形成可再流动的材料层图案以再流动可再流动的材料层图案，去除第二绝缘层和第一绝缘层 露出基板，形成隧道绝缘层。