Abstract:
A shift register includes a plurality of stages each for outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes k A-sub-stages each for controlling a voltage at an A-set node and a voltage at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.
Abstract:
A shift register includes a plurality of stages, each of which outputs a carry pulse and a scan pulse. An nth one of the stages includes a carry output switching device controlled by a voltage applied to a set node and connected between a carry clock transfer line transferring any one of i carry clock pulses and a carry output terminal of the nth stage, a scan output switching device controlled by the voltage applied to the set node and connected between a scan clock transfer line transferring any one of j scan clock pulses and a scan output terminal of the nth stage, and a stabilization switching device controlled by any one of the i carry clock pulses and connected between a carry output terminal of an (n−p)th one of the stages and the set node or between a start transfer line and the set node.
Abstract:
A shift register includes a plurality of stages, each of which outputs a carry pulse and a scan pulse. An nth one of the stages includes a carry output switching device controlled by a voltage applied to a set node and connected between a carry clock transfer line transferring any one of i carry clock pulses and a carry output terminal of the nth stage, a scan output switching device controlled by the voltage applied to the set node and connected between a scan clock transfer line transferring any one of j scan clock pulses and a scan output terminal of the nth stage, and a stabilization switching device controlled by any one of the i carry clock pulses and connected between a carry output terminal of an (n−p)th one of the stages and the set node or between a start transfer line and the set node.
Abstract:
A gate driver includes a plurality of driving units each including a first sub driving unit and a second sub driving unit, wherein output terminals of the first and second sub driving units are connected to first and second sub gate lines, respectively, and first and second sub outputs that are the outputs of the first and second sub driving units are respectively transferred to gate terminals of a first switching transistor and a second switching transistor formed in a pixel area of a display area, and wherein drain and source terminals of the first switching transistor are respectively connected to drain and source terminals of the second switching transistors.
Abstract:
Disclosed is a shift register which is an embedded shift register using an oxide transistor is capable of improving output performance, operation range and output stability, and a display device using the same. In the shift register, each stage includes at least two light shielding layers individually overlapped with the transistors of the stage by dividing the transistors into at least two regions, and a connection transistor selectively applying a voltage to a first shielding layer overlapped with the pull-up transistor of the two light shielding layers to allow the first light shielding layer to float.
Abstract:
Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.
Abstract:
Disclosed herein is a shift register which is capable of preventing leakage of charges at a set node which occurs when the duty ratio of a scan pulse is small, so as to normally output a scan pulse. The shift register includes a plurality of stages for sequentially generating outputs thereof. Each of the stages includes a carry output unit for outputting a carry pulse to drive at least one of a downstream stage and an upstream stage, and a scan output unit for outputting a scan pulse to drive a gate line. Each of the outputs generated from the stages includes the carry pulse and the scan pulse. The carry pulse and the scan pulse are paired to correspond to each other. The paired carry pulse and scan pulse have different durations.
Abstract:
Disclosed is a shift register which prevents current leakage and degradation of an oxide transistor due to light to improve output stability, and a display device using the same. The shift register includes a plurality of stages, and each stage includes a transmission line unit including a plurality of clock lines to supply a plurality of clock signals and a plurality of power lines to supply a plurality of voltages, a transistor unit including a plurality of transistors, and a light-shielding layer overlapping at least one transistor of the transistor unit so as to block light.
Abstract:
Disclosed is a shift register capable of preventing charges supplied to a Q node to turn on a pull-up transistor for outputting a scan pulse from leaking outwards. The shift register includes a plurality of stages connected to gate lines formed at a panel. Each stage includes a scan signal generator for generating a scan pulse or a turn-off signal, a scan pulse controller for generating a Q-node control signal for generation of the scan pulse, a Q-node adjuster for preventing the Q-node control signal from leaking outwards during supply of the Q-node control signal to a Q-node connected to the scan signal generator, and a turn-off signal controller for transferring a Qb-node control signal for generation of the turn-off signal to the scan signal generator via a Qb-node when no scan pulse is generated from the scan signal generator.
Abstract:
Disclosed is a shift register which is an embedded shift register using an oxide transistor is capable of improving output performance, operation range and output stability, and a display device using the same. In the shift register, each stage includes at least two light shielding layers individually overlapped with the transistors of the stage by dividing the transistors into at least two regions, and a connection transistor selectively applying a voltage to a first shielding layer overlapped with the pull-up transistor of the two light shielding layers to allow the first light shielding layer to float.