公开(公告)号：US20140229700A1

公开(公告)日：2014-08-14

申请号：US13766857

申请日：2013-02-14

Applicant: LSI CORPORATION

Inventor： Shaohua Yang ,  Fan Zhang ,  Kaitlyn T. Nguyen

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0676

Abstract: Systems and methods for data processing particularly related addressing latency concerns in relation to data processing.

Abstract translation: 用于数据处理的系统和方法特别涉及解决与数据处理相关的延迟问题。

公开(公告)号：US20140157074A1

公开(公告)日：2014-06-05

申请号：US13692908

申请日：2012-12-03

Applicant: LSI Corporation

Inventor： Fan Zhang ,  Kaitlyn T. Nguyen ,  Jun Xiao

IPC: G06F11/00

CPC classification number: G06F11/0763 ,  G06F11/0727 ,  G06F11/1443 ,  G11B20/10527 ,  G11B20/18 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3738 ,  H03M13/3746 ,  H03M13/3753 ,  H03M13/6325 ,  H03M13/6343

Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for re-processing data sets not successfully processed during standard processing.

Abstract translation: 与用于数据处理的系统和方法相关的系统，电路，设备和/或方法，更具体地涉及用于重新处理在标准处理期间未成功处理的数据集的系统和方法。

公开(公告)号：US20140130061A1

公开(公告)日：2014-05-08

申请号：US13667450

申请日：2012-11-02

Applicant: LSI CORPORATION

Inventor： Zongwang Li ,  Chung-Li Wang ,  Kaitlyn T. Nguyen ,  Keklik Bayam Alptekin

IPC: G06F9/54

CPC classification number: G06F9/30145 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/616 ,  H03M13/6566

Abstract: The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a converted CNU message having sub-circulants sized for RAM-based processing. The decoder further includes RAM configured to store sub-circulants of the converted CNU message at addressable memory blocks for parallel VNU processing.

Abstract translation: 本公开涉及一种利用随机存取存储器（RAM）存储和处理校验节点单元（CNU）消息的系统和方法。 解码器包括CNU的分层阵列，其被配置为接收与解码器正在操作的至少一个数据段的解码比特相关联的至少一个可变节点单元（VNU）消息。 解码器还包括CNU消息转换器，其被配置为置换VNU消息的至少一个初始循环，以生成具有基于RAM的处理的子循环的转换的CNU消息。 解码器还包括RAM，其被配置为将转换的CNU消息的子循环存储在可寻址存储器块处以用于并行VNU处理。