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    Slice formatting and interleaving for interleaved sectors
    1.
    发明授权
    Slice formatting and interleaving for interleaved sectors 有权
    交错扇区的切片格式化和交织

    公开(公告)号：US09304910B2

    公开(公告)日：2016-04-05

    申请号：US14153154

    申请日：2014-01-13

    Applicant: LSI Corporation

    Inventor： Qi Zuo ,  Kuhong Jeong ,  Shu Li ,  Xiang Wang ,  Han Fang ,  Shaohua Yang

    IPC: G06F12/06

    CPC classification number: G06F12/0607

    Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.

    Abstract translation: 公开了一种用于在存储系统中交织多个逻辑扇区的存储系统和方法。 该方法包括：将每个逻辑扇区划分成预定数量的片; 顺序索引逻辑扇区，其中每个逻辑扇区由逻辑扇区索引标识; 顺序索引每个逻辑扇区中的预定数量的片，其中预定数量片的每个片由每个逻辑扇区内的片索引识别; 以及根据片交织处理对逻辑扇区进行交织。 交错步骤还包括：a）将第一索引逻辑扇区的第一索引片段识别为初始片段; 以及b）通过将切片索引推进到切片索引序列中的后续索引并且将逻辑扇区索引推进到逻辑扇区索引序列中的后续索引来识别随后的片段。

    Systems and methods for reduced constraint code data processing
    2.
    发明授权
    Systems and methods for reduced constraint code data processing 有权
    用于减少约束代码数据处理的系统和方法

    公开(公告)号：US09281843B2

    公开(公告)日：2016-03-08

    申请号：US13853711

    申请日：2013-03-29

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Anatoli A. Bolotov ,  Shaohua Yang ,  Fan Zhang

    IPC: H03M13/11 ,  H03M13/29 ,  H03M13/00 ,  G11B20/18

    CPC classification number: H03M13/116 ,  G11B20/1833 ,  H03M13/1111 ,  H03M13/1171 ,  H03M13/2957 ,  H03M13/6325 ,  H03M13/6343

    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. In one case a data processing system is disclosed that includes a decoder circuit operable to apply a low density parity check algorithm to a decoder input to yield an interim decoded output, where the decoder input is a codeword formed of two bit symbols, and where the decoder input is encoded to yield a last layer including at least two different entry values. In addition, the data processing system includes an inverse mapping circuit operable to remap the interim decoded output to yield an overall decoded output.

    Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于执行数据解码的系统和方法。 在一种情况下，公开了一种数据处理系统，其包括解码器电路，其可操作以将低密度奇偶校验算法应用于解码器输入以产生中间解码输出，其中解码器输入是由两个比特符号形成的码字，并且其中 解码器输入被编码以产生包括至少两个不同入口值的最后一层。 另外，该数据处理系统包括一个反向映射电路，可操作用于重新映射中间解码的输出以产生一个整体解码的输出。

    Multi-Level Enumerative Encoder And Decoder
    3.
    发明申请
    Multi-Level Enumerative Encoder And Decoder 有权
    多级枚举编码器和解码器

    公开(公告)号：US20150380050A1

    公开(公告)日：2015-12-31

    申请号：US14318665

    申请日：2014-06-29

    Applicant: LSI Corporation

    Inventor： Victor Krachkovsky ,  Razmik Karabed ,  Shaohua Yang ,  Wu Chang

    IPC: G11B20/12

    CPC classification number: G11B20/1217 ,  G11B20/1833 ,  H03M7/4006 ,  H03M13/1102

    Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.

    Abstract translation: 存储系统包括可操作以保持数据集的存储介质，可操作以将数据集写入存储介质并从存储介质读取数据集的读/写头组件，可操作以编码的多级枚举编码器 其前的数据集作为编码数据被写入存储介质，其中该枚举编码器使用多个依赖于水平的基站来应用枚举，以及解码器，用于在从存储介质读取数据集之后对其进行解码。

    Gated noise-predictive filter calibration
    4.
    发明授权
    Gated noise-predictive filter calibration 有权
    门控噪声预测滤波器校准

    公开(公告)号：US09202514B1

    公开(公告)日：2015-12-01

    申请号：US14334410

    申请日：2014-07-17

    Applicant: LSI Corporation

    Inventor： Jianzhong Huang ,  Shaohua Yang ,  Haitao Xia ,  Fuminori Sai ,  Weijun Tan

    IPC: G11B5/09 ,  G11B5/035 ,  G11B20/10

    CPC classification number: G11B20/10046

    Abstract: An apparatus for calibrating a noise predictive filter includes a noise-predictive filter operable to filter digital data samples to yield filtered data samples, a calibration circuit operable to calculate tap coefficients for the noise-predictive filter based at least in part on the digital data samples, and a gating circuit operable to select a portion of the digital data samples for use by the calibration circuit in calculating the tap coefficients.

    Abstract translation: 用于校准噪声预测滤波器的装置包括噪声预测滤波器，其可操作以对数字数据样本进行滤波以产生经滤波的数据采样;校准电路，可用于至少部分地基于数字数据样本来计算噪声预测滤波器的抽头系数 以及门控电路，其可操作以选择数字数据样本的一部分，以供校准电路在计算抽头系数时使用。

    Systems and methods for data retry using averaging process
    6.
    发明授权
    Systems and methods for data retry using averaging process 有权
    使用平均过程进行数据重试的系统和方法

    公开(公告)号：US09190104B2

    公开(公告)日：2015-11-17

    申请号：US13802627

    申请日：2013-03-13

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Kapil Gaba ,  Yoon L. Liow ,  Xuebin Wu ,  Qi Zuo ,  YuQing Yang ,  Lei Wang

    IPC: G06F17/10 ,  G11B20/10

    CPC classification number: G11B20/10046

    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing. As an example, a data processing system is discussed that includes a sample averaging circuit operable to average digital samples from an analog to digital converter circuit over multiple instances of an analog input to yield an X-average output, and a selector circuit operable to select one of the digital samples or the X-average output as a processing output.

    Abstract translation: 实施例涉及用于数据处理的系统和方法，更具体地涉及在数据处理期间用于校准的系统和方法。 作为示例，讨论了一种数据处理系统，其包括采样平均电路，其可操作以在模拟输入的多个实例上平均来自模数转换器电路的数字采样以产生X平均输出，以及可操作以选择 数字样本之一或X平均输出作为处理输出。

    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
    7.
    发明授权
    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
    用于读通道的可编程准循环低密度奇偶校验（QC LDPC）编码器

    公开(公告)号：US09166622B2

    公开(公告)日：2015-10-20

    申请号：US13632768

    申请日：2012-10-01

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    IPC: H03M13/00 ,  H03M13/05 ,  H03M13/11 ,  G06F11/10 ,  H03M13/27

    CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

    Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

    Systems and methods for enhanced local iteration randomization in a data decoder
    8.
    发明授权
    Systems and methods for enhanced local iteration randomization in a data decoder 有权
    用于数据解码器中增强的局部迭代随机化的系统和方法

    公开(公告)号：US09112531B2

    公开(公告)日：2015-08-18

    申请号：US13652012

    申请日：2012-10-15

    Applicant: LSI Corporation

    Inventor： Fan Zhang ,  Wu Chang ,  Shaohua Yang ,  Ming Jin

    IPC: H03M13/05 ,  H03M13/00 ,  H03M13/11 ,  H03M13/41

    CPC classification number: H03M13/1128 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1142 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6343

    Abstract: Systems and methods for data processing particularly related local iteration randomization in a data decoding circuit. In some cases a data processing system may include: a layered data decoding circuit, a value generator circuit, and a selector circuit. The layered data decoding circuit is configured to iteratively apply a data decoding algorithm up to a selected number of times to a decoder input to yield a decoded output in accordance with a layer order. The value generator circuit is operable configured to generate an adjusted number of times where the adjusted number of times is less than a default number of times. The selector circuit is operable configured to select one of the default number of times and the adjusted number of times as the selected number of times.

    Abstract translation: 用于数据处理的系统和方法特别涉及数据解码电路中的局部迭代随机化。 在一些情况下，数据处理系统可以包括：分层数据解码电路，值产生器电路和选择器电路。 分层数据解码电路被配置为将数据解码算法迭代地应用到解码器输入的选定次数，以根据层次顺序产生解码的输出。 值产生器电路可操作地配置为产生经调整次数小于默认次数的调整次数。 选择器电路可操作地配置为选择默认次数和调整次数中的一个作为所选次数。

    SYSTEM AND METHOD TO INTERLEAVE MEMORY
    9.
    发明申请
    SYSTEM AND METHOD TO INTERLEAVE MEMORY 有权
    用于记忆的系统和方法

    公开(公告)号：US20150154114A1

    公开(公告)日：2015-06-04

    申请号：US14169424

    申请日：2014-01-31

    Applicant: LSI Corporation

    Inventor： Yang Han ,  Zongwang Li ,  Shaohua Yang ,  Kaichi Zhang

    IPC: G06F12/06

    CPC classification number: G06F12/0607 ,  G11C7/1012 ,  G11C7/1042

    Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.

    Abstract translation: 存储器交错装置包括第一和第二交织器。 第一交织器响应于扇区选择信号选择性地交织存储在第一存储器中的信息。 第二交织器响应于扇区选择信号选择性地交织存储在第二存储器中的信息。 第一交织器与第二交织器耦合。 存储器交错系统包括交织器和存储装置。 交织器与第一扇区尺寸和第二扇区尺寸相关联。 交织器响应于扇区选择信号选择性地交织存储在第一存储器和/或第二存储器中的信息。 存储装置响应于扇区选择信号选择性地向交织器提供第一掩蔽种子和/或第二掩蔽种子。 还公开了相应的方法。

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