Memory architecture for layered low-density parity-check decoder
    3.
    发明授权
    Memory architecture for layered low-density parity-check decoder 有权
    分层低密度奇偶校验解码器的内存架构

    公开(公告)号:US09037952B2

    公开(公告)日:2015-05-19

    申请号:US13760609

    申请日:2013-02-06

    Abstract: A hard decision memory interacts with a multi-layered low-density parity-check decoder by sending multiple L values and E values to a multi-layered low-density parity-check decoder (LDPC), and the L value E value hard decision memory (LE hard decision memory) receives one or more hard decisions. The LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. The use of the LE hard decision memory results improved multi-level LDPC decoding of an LDPC encoded message.

    Abstract translation: 硬判决存储器通过向多层低密度奇偶校验解码器(LDPC)发送多个L值和E值与多层低密度奇偶校验解码器相互作用,并且L值E值硬判决存储器 (LE硬决策存储器)接收一个或多个硬判决。 LE硬判决存储器包括全局映射元件,用于交织来自第一和第二循环的L值,并将交织的值存储在第一存储器元件中。 然后,低密度奇偶校验解码器处理来自第一存储器元件的循环并将输出存储在第二存储元件中。 LE硬决策存储器不包括任何多路复用单元。 LE硬判决存储器的使用结果改进了LDPC编码消息的多级LDPC解码。

    System and Method for Check-Node Unit Message Processing
    5.
    发明申请
    System and Method for Check-Node Unit Message Processing 有权
    用于检查节点单元消息处理的系统和方法

    公开(公告)号:US20140130061A1

    公开(公告)日:2014-05-08

    申请号:US13667450

    申请日:2012-11-02

    Abstract: The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a converted CNU message having sub-circulants sized for RAM-based processing. The decoder further includes RAM configured to store sub-circulants of the converted CNU message at addressable memory blocks for parallel VNU processing.

    Abstract translation: 本公开涉及一种利用随机存取存储器(RAM)存储和处理校验节点单元(CNU)消息的系统和方法。 解码器包括CNU的分层阵列,其被配置为接收与解码器正在操作的至少一个数据段的解码比特相关联的至少一个可变节点单元(VNU)消息。 解码器还包括CNU消息转换器,其被配置为置换VNU消息的至少一个初始循环,以生成具有基于RAM的处理的子循环的转换的CNU消息。 解码器还包括RAM,其被配置为将转换的CNU消息的子循环存储在可寻址存储器块处以用于并行VNU处理。

    MODIFIED TARGETED SYMBOL FLIPPING FOR NON-BINARY LDPC CODES
    6.
    发明申请
    MODIFIED TARGETED SYMBOL FLIPPING FOR NON-BINARY LDPC CODES 有权
    用于非二进制LDPC编码的修改的目标符号转移

    公开(公告)号:US20140095954A1

    公开(公告)日:2014-04-03

    申请号:US13629726

    申请日:2012-09-28

    CPC classification number: H03M13/1108 H03M13/3738

    Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

    Abstract translation: LDPC解码器包括用于不满足检查的LDPC码字中的可疑比特的目标符号翻转的处理器。 检查索引和可变索引的所有组合被编译并且相关联到目标符号翻转候选的池中,并且与符号索引一起返回到使用这样的符号索引来识别符号以便打破陷阱集合的过程。

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