Abstract:
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
Abstract:
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
Abstract:
A hard decision memory interacts with a multi-layered low-density parity-check decoder by sending multiple L values and E values to a multi-layered low-density parity-check decoder (LDPC), and the L value E value hard decision memory (LE hard decision memory) receives one or more hard decisions. The LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. The use of the LE hard decision memory results improved multi-level LDPC decoding of an LDPC encoded message.
Abstract:
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process.
Abstract:
The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a converted CNU message having sub-circulants sized for RAM-based processing. The decoder further includes RAM configured to store sub-circulants of the converted CNU message at addressable memory blocks for parallel VNU processing.
Abstract:
A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.
Abstract:
The present inventions are related to systems and methods for an LDPC decoder with fractional local iterations that may be used in a data processing system with an LDPC decoder and data detector to better balance processing times in the LDPC decoder and data detector.
Abstract:
A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages.
Abstract:
A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages.
Abstract:
A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.