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公开(公告)号：US07944932B2
公开(公告)日：2011-05-17
申请号：US12060751
申请日：2008-04-01
IPC分类号： H04L12/28 , G06F15/173 , G06F15/76 , G06F15/00
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.
摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个处理单元接收的操作广播到多个处理单元中的一个或多个 处理单位。
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12.发明授权Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope 失效数据处理系统，缓存系统和精确形成指示广播范围的无效一致性状态的方法公开(公告)号：US07512742B2
公开(公告)日：2009-03-31
申请号：US11333615
申请日：2006-01-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。 如果分配了与存储器块相关联的地址的归属系统存储器在第一相关域内，则确定。 如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成 一致性状态下，内存块被缓存在第一个相干域之外。
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13.发明申请Data Processing System, Method and Interconnect Fabric that Protect Ownership Transfer with Non-Uniform Protection Windows 有权数据处理系统，方法和互连结构，保护所有权转移与非均匀保护Windows公开(公告)号：US20080120625A1
公开(公告)日：2008-05-22
申请号：US11560619
申请日：2006-11-16
IPC分类号： G06F9/44
CPC分类号： G06F15/173
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.
摘要翻译： 在数据处理系统中，多个代理之间进行通信。 每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。 观察到请求的延迟和多个代理之间的组合响应。 通过参考所观察到的延迟，多个代理中的每个被配置有保护窗口扩展的相应持续时间。 每个保护窗口扩展是在绞盘期间接收到组合响应之后的周期，多个代理之一相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。 多个代理根据配置使用保护窗口扩展，并且至少两个代理具有不同持续时间的保护窗口扩展。
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14.发明授权Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务公开(公告)号：US07447845B2
公开(公告)日：2008-11-04
申请号：US11457333
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译： 数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。 多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求， 它能够维修。
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15.发明申请Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced on a Fixed Schedule 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求在固定时间表上服务公开(公告)号：US20080016278A1
公开(公告)日：2008-01-17
申请号：US11457322
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译： 处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录。 缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑 其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。 调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。
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16.发明授权Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求以固定的时间表被服务公开(公告)号：US07447844B2
公开(公告)日：2008-11-04
申请号：US11457322
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译： 处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录。 缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑 其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。 调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。
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17.发明申请Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced by State Machines with Differing Functionality 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务公开(公告)号：US20080016279A1
公开(公告)日：2008-01-17
申请号：US11457333
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译： 数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。 多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求， 它能够维修。
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公开(公告)号：US07734876B2
公开(公告)日：2010-06-08
申请号：US11560603
申请日：2006-11-16
申请人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/0833
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Within data storage in the data processing system, a data structure indicates a duration of a protection window extension for each of the plurality of agents. Each protection window extension is a period following receipt of a combined response during which an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. Each of the plurality of agents is configured with a duration of a protection window extension by reference to the data structure, and at least two of the agents have protection window extensions of differing durations. The plurality of agents thereafter employ the configured protection window extensions.
摘要翻译： 在数据处理系统中，多个代理之间进行通信。 每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。 在数据处理系统中的数据存储中，数据结构指示多个代理中的每一个的保护窗口扩展的持续时间。 每个保护窗口扩展是接收到组合响应之后的周期，在该周期期间，所述多个代理中的相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。 通过参考数据结构，多个代理中的每一个配置有保护窗口扩展的持续时间，并且至少两个代理具有不同持续时间的保护窗口扩展。 此后，多个代理程序采用配置的保护窗口扩展。
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19.发明授权Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory 有权数据处理系统和方法，用于使用存储器的位置预测性地选择操作的广播范围公开(公告)号：US07454578B2
公开(公告)日：2008-11-18
申请号：US11055697
申请日：2005-02-10
申请人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
摘要翻译： 高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。 第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。 主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。
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20.发明授权Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes 失效允许I / O写入操作和多个操作范围的流水线的数据处理系统和方法公开(公告)号：US07725619B2
公开(公告)日：2010-05-25
申请号：US11226967
申请日：2005-09-15
申请人： George W. Daly, Jr. , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： George W. Daly, Jr. , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.
摘要翻译： 数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控制器的第二处理。 存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。 响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。 响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点 与第二个地址关联的域指示符。
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