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    CAPACITIVE ISOLATED VOLTAGE DOMAINS
    12.
    发明申请
    CAPACITIVE ISOLATED VOLTAGE DOMAINS 有权
    电容式隔离电压域

    公开(公告)号：US20130279550A1

    公开(公告)日：2013-10-24

    申请号：US13454739

    申请日：2012-04-24

    申请人： Hendrik Boezen ,  Martijn Bredius

    发明人： Hendrik Boezen ,  Martijn Bredius

    IPC分类号： H04L27/04 ,  H04L27/06 ,  H04B1/38

    CPC分类号： H03M5/04 ,  H03M5/08 ,  H04B5/0012 ,  H04B14/026 ,  H04L25/0266

    摘要： In one embodiment, a method of communicating data values over a three conductor interface is provided. Different data values are transmitted by generating and transmitting three respective signals to a receiver using three conductors. The first signal is maintained as a set voltage level. The second signal is alternated between a high voltage and a low voltage according to a carrier frequency. The third signal is alternated between the high and low voltages and is out of phased with the second signal. To transmit a first data value, the first signal is generated on a first conductor, the second signal is generated on a second conductor, and the third signal is generated on a third conductor. To transmit a second data value, the second signal is generated on the first conductor, the first signal is generated on the second conductor, and the third signal is generated on the third conductor.

    摘要翻译： 在一个实施例中，提供了一种在三导体接口上传送数据值的方法。 通过使用三个导体生成和发送三个相应信号到接收机来发送不同的数据值。 第一信号被保持为设定电压电平。 第二信号根据载波频率在高电压和低电压之间交替。 第三信号在高电压和低电压之间交替，并且与第二信号相分离。 为了发送第一数据值，第一信号在第一导体上产生，第二信号在第二导体上产生，并且第三信号在第三导体上产生。 为了发送第二数据值，在第一导体上产生第二信号，在第二导体上产生第一信号，并且在第三导体上产生第三信号。

    Electronic sensing circuit that compensates for reference voltage drift
    13.
    发明授权
    Electronic sensing circuit that compensates for reference voltage drift 有权
    补偿参考电压漂移的电子感应电路

    公开(公告)号：US07301330B2

    公开(公告)日：2007-11-27

    申请号：US10572106

    申请日：2004-09-09

    申请人： Jacobus Adrianus Van Oevelen ,  Stefan Butzmann ,  Reinhard Buchhold ,  Thomas Stork ,  Hendrik Boezen

    发明人： Jacobus Adrianus Van Oevelen ,  Stefan Butzmann ,  Reinhard Buchhold ,  Thomas Stork ,  Hendrik Boezen

    IPC分类号： G01B7/30

    CPC分类号： G01D3/02

    摘要： A sensor (10) has an output coupled to a first comparator input. A control circuit (18) is arranged to switch from an upward tracking mode to a downward relative level detection mode, to a downward tracking mode, to an upward relative level detection mode and back to the upward tracking mode successively. A first and second digital to analog conversion circuit (14a,b) receive a first and second digital control value from the control circuit (18) respectively. A controllable combiner circuit (16) has inputs coupled to outputs of the first and second digital to analog conversion circuits (14a,b) and an output coupled to the second comparator input, the control circuit (18) having first output coupled to controllable combiner circuit (16) to cause the combiner circuit (16) to supply first and second combiner output signals determined by the first and second digital to analog conversion circuit (14a,b) to the second comparator input in the upward and downward tracking mode respectively, and to supply a third combiner output signal corresponding to an average of the first and second combiner output signals to the second comparator input in the relative level detection modes. The control circuit (18) has an input coupled to the output of the comparator (12), the control circuit (18) controlling one directional upward tracking by the first digital to analog conversion circuit (14a) of upward changes of the sensing signal in the upward tracking mode, and controlling one directional downward tracking by the second digital to analog conversion circuit (14b) Of downward changes of the sensing signal in the upward tracking mode.

    摘要翻译： 传感器（10）具有耦合到第一比较器输入的输出。 控制电路（18）被布置成从向上跟踪模式向下相对电平检测模式切换到向下跟踪模式，向上相对电平检测模式并且依次返回到向上跟踪模式。 第一和第二数模转换电路（14a，b）分别从控制电路（18）接收第一和第二数字控制值。 可控组合器电路（16）具有耦合到第一和第二数模转换电路（14a，b）的输出和耦合到第二比较器输入的输出的输入，该控制电路（18）具有耦合到可控制 组合器电路（16）使得组合器电路（16）以上下跟踪模式将第一和第二数模转换电路（14a，b）确定的第一和第二组合器输出信号提供给第二比较器输入端 并且在相对电平检测模式中将与第一和第二组合器输出信号的平均值对应的第三组合器输出信号提供给第二比较器输入。 控制电路（18）具有耦合到比较器（12）的输出端的输入端，控制电路（18）控制第一数模转换电路（14a）向感测信号向上变化的一个方向向上跟踪 在向上跟踪模式中，并且通过第二数模转换电路（14b）控制向上跟踪模式中感测信号的向下变化的一个方向向下跟踪。

    Line driver with current source output and high immunity to RF signals
    14.
    发明授权
    Line driver with current source output and high immunity to RF signals 有权
    具有电流源输出的线路驱动器和对RF信号的高抗扰度

    公开(公告)号：US06949963B2

    公开(公告)日：2005-09-27

    申请号：US10095348

    申请日：2002-03-11

    申请人： Clemens Gerhardus Johannes De Haas ,  Hendrik Boezen ,  Aloysius Johannes Maria Boomkamp ,  Gerrit Jan Bollen ,  Abraham Klaas Van Den Heuvel ,  Ruurd Anne Visser

    发明人： Clemens Gerhardus Johannes De Haas ,  Hendrik Boezen ,  Aloysius Johannes Maria Boomkamp ,  Gerrit Jan Bollen ,  Abraham Klaas Van Den Heuvel ,  Ruurd Anne Visser

    IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/0175 ,  H04L25/02 ,  H03K3/00

    CPC分类号： H04L25/028

    摘要： Line driver for a LIN-bus. The line driver has a current source output transistor (T1) for pulling down the LIN-bus wire (LB) to ground (GND). The LIN-bus wire (LB) is connected to a positive supply voltage (VBAT) through a pull-up resistor (R1). The output transistor (T1) is driven by a driver stage (DRV) in response to an input current (J1) at an input node (X). The driver stage has a further resistor (R2) connected between the gate of the output transistor (T1) and a reference terminal (GND), a reference transistor (T2) which has its source connected to the reference terminal (GND) and its drain coupled to the input node (X); the gates of the output transistor (T1) and the reference transistor (T2) are connected to an output (DAO1) of a differential amplifier (DA1) which has an inverting input (DAN1) coupled to a bias voltage source (E2) and a non-inverting input (DAP1) coupled to the input node (X). The further resistor (R2) stage provides a low-impedance path to ground for RF disturbances reaching the gate of the output transistor (T1) through the drain-gate capacitance of the output transistor (T1) and prevents these disturbances from penetrating the driver stage.

    摘要翻译： 用于LIN总线的线路驱动器。 线路驱动器具有用于将LIN总线（LB）拉到地（GND）的电流源输出晶体管（T 1）。 LIN总线（LB）通过上拉电阻（R 1）连接到正电源电压（VBAT）。 响应于输入节点（X）处的输入电流（J 1），输出晶体管（T 1）由驱动级（DRV）驱动。 驱动级具有连接在输出晶体管（T 1）的栅极和参考端子（GND）之间的另一个电阻器（R 2），其源极连接到参考端子（GND）的参考晶体管（T 2） 并且其漏极耦合到输入节点（X）; 输出晶体管（T 1）和参考晶体管（T 2）的栅极连接到差分放大器（DA 1）的输出（DAO 1），差分放大器（DA 1）具有耦合到偏置电压源 （E 2）和耦合到输入节点（X）的非反相输入（DAP 1）。 另外的电阻器（R 2）级通过输出晶体管（T 1）的漏极 - 栅极电容为RF输入端到达输出晶体管（T 1）的栅极提供了一个低阻抗路径，并防止这些干扰穿透 司机舞台。

    Circuit for suppressing a common mode component in a signal from a CAN communication bus
    16.
    发明授权
    Circuit for suppressing a common mode component in a signal from a CAN communication bus 有权
    用于抑制来自CAN通信总线的信号中的共模分量的电路

    公开(公告)号：US06326817B1

    公开(公告)日：2001-12-04

    申请号：US09561473

    申请日：2000-04-27

    申请人： Hendrik Boezen ,  Abraham Klaas Van Den Heuvel

    发明人： Hendrik Boezen ,  Abraham Klaas Van Den Heuvel

    IPC分类号： H03R5153

    CPC分类号： H03F3/45704 ,  H04L12/4135 ,  H04L2012/40215

    摘要： The common mode component in the difference signal on the bus terminals (2, 4) of a CAN bus is counteracted by four transistors (M1-M4) connected between the supply terminals (28, 32) and a center tap (16) of a voltage divider (6A, 6B, 8, 10, 12A, 12B) between the bus terminals (2, 4). As a result of this, the voltage on the center tap (16) varies to a substantially smaller extent or not at all. Thus, it is possible to use a simpler differential amplifier (20) having a smaller common mode swing at the inputs (22, 24). Moreover, the attenuation factor selected for the voltage divider can be smaller, as a result of which a higher difference voltage is available for the differential amplifier (20).

    摘要翻译： CAN总线的总线端子（2,4）上的差分信号中的共模分量由连接在供电端子（28,32）和中心抽头（16）之间的四个晶体管（M1-M4）抵消， 在总线端子（2,4）之间的分压器（6A，6B，8,10，12A，12B）。 结果，中心抽头（16）上的电压变化到很小程度，或根本不变。 因此，可以使用在输入端（22,24）处具有较小共模摆幅的更简单的差分放大器（20）。 此外，为分压器选择的衰减因子可以更小，因此差分放大器（20）可以使用较高的差分电压。

    CAN bus driver with symmetrical differential output signals
    17.
    发明授权
    CAN bus driver with symmetrical differential output signals 有权
    具有对称差分输出信号的CAN总线驱动器

    公开(公告)号：US6154061A

    公开(公告)日：2000-11-28

    申请号：US304596

    申请日：1999-05-04

    申请人： Hendrik Boezen ,  Martinus Bredius ,  Aloysius J. M. Boomkamp ,  Cecilius G. Kwakernaat ,  Abraham K. Van Den Heuvel

    发明人： Hendrik Boezen ,  Martinus Bredius ,  Aloysius J. M. Boomkamp ,  Cecilius G. Kwakernaat ,  Abraham K. Van Den Heuvel

    IPC分类号： G06F3/00 ,  H03K3/00 ,  H04L25/02 ,  H03K19/0175

    CPC分类号： H04L25/028 ,  H04L25/0276

    摘要： Bus driver having a P-channel output transistor (T1) for driving a first bus terminal (6) from a positive supply terminal (2), an N-channel output transistor (T2) for driving a second bus terminal (12) from a negative supply terminal (4), a P-channel driver transistor (T3) and an N-channel driver transistor (T4) series connected between the positive (2) and the negative (4) supply terminal. The control electrodes of the P-channel transistors (T1, T3) are interconnected and the control electrodes of the N-channel transistors (T2, T4) are interconnected to obtain a fixed relationship between the currents through the P-channel transistors (T1, T3) and through the N-channel transistors (T2, T4). The conduction of the driver transistors (T3, T4) is controlled by two floating control voltage sources (22, 24) which are connected between the interconnection node (20) of the driver transistors (T3, T4) and the respective control electrodes of the driver transistors. Any difference between the current through the P-channel driver transistor (T3) and the N-channel driver transistor (T4) is compensated for by a change in the voltage level at the interconnection node (20). In this way the currents through the driver transistors (T3, T4), and also through the output transistors (T1, T2) which are scaled copies of the driver transistors, are always equal and a highly symmetrical driving of the two bus wires (8, 14) is obtained. As a result, the electromagnetic radiation of the bus wires is low.

    摘要翻译： 具有用于从正电源端子（2）驱动第一总线端子（6）的P沟道输出晶体管（T1）的总线驱动器，用于从第二总线端子（12）驱动的N沟道输出晶体管（T2） 负电源端子（4），串联连接在正（2）和负（4）电源端子之间的P沟道驱动晶体管（T3）和N沟道驱动晶体管（T4）。 P沟道晶体管（T1，T3）的控制电极互连，并且N沟道晶体管（T2，T4）的控制电极互连，以获得通过P沟道晶体管（T1，T3）的电流之间的固定关系， T3）并通过N沟道晶体管（T2，T4）。 驱动晶体管（T3，T4）的导通由两个浮动控制电压源（22,24）控制，这两个浮动控制电压源连接在驱动晶体管（T3，T4）的互连节点（20）和相应的控制电极 驱动晶体管。 通过P沟道驱动晶体管（T3）的电流和N沟道驱动晶体管（T4）之间的任何差异都由互连节点（20）上的电压电平的变化来补偿。 以这种方式，通过驱动晶体管（T3，T4）的电流以及驱动晶体管的缩放副本的输出晶体管（T1，T2）总是相等的，并且两条母线（8 ，14）。 结果，母线的电磁辐射较低。

    Balanced voltage-to-current converter with quiescent current control
    18.
    发明授权
    Balanced voltage-to-current converter with quiescent current control 失效
    具有静态电流控制的平衡电压 - 电流转换器

    公开(公告)号：US5497074A

    公开(公告)日：1996-03-05

    申请号：US227829

    申请日：1994-04-14

    申请人： Hendrik Boezen

    发明人： Hendrik Boezen

    IPC分类号： H03F3/34 ,  G05F1/56 ,  H03F3/45 ,  G05F3/26

    CPC分类号： H03F3/45479 ,  G05F1/56

    摘要： A balanced voltage-to-current converter has two cells. Each cell has a first input terminal coupled to a first current source via a diode-connected first transistor and to an output terminal via the main current path of a third transistor, and a second input terminal coupled to a second (controllable) current source via the main current path of a second transistor. The control electrode of the third transistor is connected to the node between the second current source and the second transistor. The first input terminal of one of cell is connected to the second input terminal of the other cell and vice versa. The quiescent current through the third transistor is controlled by a differential amplifier which compares the voltage difference between the control electrode and a first main electrode of the third transistor with a reference voltage which is representative of the current through the third transistor. The output signals of the differential amplifiers are summed in an adder and are applied to control inputs of the second current sources.

    摘要翻译： 平衡电压 - 电流转换器有两个单元。 每个单元具有经由二极管连接的第一晶体管耦合到第一电流源的第一输入端和经由第三晶体管的主电流通路连接到输出端的第一输入端，以及耦合到第二（可控）电流源的第二输入端， 第二晶体管的主电流通路。 第三晶体管的控制电极连接到第二电流源和第二晶体管之间的节点。 单元之一的第一输入端连接到另一单元的第二输入端，反之亦然。 通过第三晶体管的静态电流由差分放大器控制，该差分放大器将控制电极和第三晶体管的第一主电极之间的电压差与代表通过第三晶体管的电流的参考电压进行比较。 差分放大器的输出信号在加法器中相加，并被施加到第二电流源的控制输入。

    Capacitive isolated voltage domains
    19.
    发明授权
    Capacitive isolated voltage domains 有权
    电容隔离电压域

    公开(公告)号：US08787502B2

    公开(公告)日：2014-07-22

    申请号：US13454739

    申请日：2012-04-24

    申请人： Hendrik Boezen ,  Martijn Bredius

    发明人： Hendrik Boezen ,  Martijn Bredius

    IPC分类号： H04L25/06

    CPC分类号： H03M5/04 ,  H03M5/08 ,  H04B5/0012 ,  H04B14/026 ,  H04L25/0266

    摘要： In one embodiment, a method of communicating data values over a three conductor interface is provided. Different data values are transmitted by generating and transmitting three respective signals to a receiver using three conductors. The first signal is maintained as a set voltage level. The second signal is alternated between a high voltage and a low voltage according to a carrier frequency. The third signal is alternated between the high and low voltages and is out of phased with the second signal. To transmit a first data value, the first signal is generated on a first conductor, the second signal is generated on a second conductor, and the third signal is generated on a third conductor. To transmit a second data value, the second signal is generated on the first conductor, the first signal is generated on the second conductor, and the third signal is generated on the third conductor.

    摘要翻译： 在一个实施例中，提供了一种在三导体接口上传送数据值的方法。 通过使用三个导体生成和发送三个相应信号到接收机来发送不同的数据值。 第一信号被保持为设定电压电平。 第二信号根据载波频率在高电压和低电压之间交替。 第三信号在高电压和低电压之间交替，并且与第二信号相分离。 为了发送第一数据值，第一信号在第一导体上产生，第二信号在第二导体上产生，并且第三信号在第三导体上产生。 为了发送第二数据值，在第一导体上产生第二信号，在第二导体上产生第一信号，并且在第三导体上产生第三信号。

    Electronic sensing circuit
    20.
    发明申请
    Electronic sensing circuit 有权
    电子感应电路

    公开(公告)号：US20070059936A1

    公开(公告)日：2007-03-15

    申请号：US10572106

    申请日：2004-09-09

    申请人： Jacobus Van Oevelen ,  Stefan Butzmann ,  Reinhard Buchhold ,  Thomas Stork ,  Hendrik Boezen

    发明人： Jacobus Van Oevelen ,  Stefan Butzmann ,  Reinhard Buchhold ,  Thomas Stork ,  Hendrik Boezen

    IPC分类号： C03C15/00 ,  H01L21/306 ,  H01L21/302 ,  H01L21/461

    CPC分类号： G01D3/02

    摘要： A sensor (10) has an output coupled to a first comparator input. A control circuit (18) is arranged to switch from an upward tracking mode to a downward relative level detection mode, to a downward tracking mode, to an upward relative level detection mode and back to the upward tracking mode successively. A first and second digital to analog conversion circuit (14a,b) receive a first and second digital control value from the control circuit (18) respectively. A controllable combiner circuit (16) has inputs coupled to outputs of the first and second digital to analog conversion circuits (14a,b) and an output coupled to the second comparator input, the control circuit (18) having first output coupled to controllable combiner circuit (16) to cause the combiner circuit (16) to supply first and second combiner output signals determined by the first and second digital to analog conversion circuit (14a,b) to the second comparator input in the upward and downward tracking mode respectively, and to supply a third combiner output signal corresponding to an average of the first and second combiner output signals to the second comparator input in the relative level detection modes. The control circuit (18) has an input coupled to the output of the comparator (12), the control circuit (18) controlling one directional upward tracking by the first digital to analog conversion circuit (14a) of upward changes of the sensing signal in the upward tracking mode, and controlling one directional downward tracking by the second digital to analog conversion circuit (14b) Of downward changes of the sensing signal in the upward tracking mode.

    摘要翻译： 传感器（10）具有耦合到第一比较器输入的输出。 控制电路（18）被布置成从向上跟踪模式向下相对电平检测模式切换到向下跟踪模式，向上相对电平检测模式并且依次返回到向上跟踪模式。 第一和第二数模转换电路（14a，b）分别从控制电路（18）接收第一和第二数字控制值。 可控组合器电路（16）具有耦合到第一和第二数模转换电路（14a，b）的输出和耦合到第二比较器输入的输出的输入，该控制电路（18）具有耦合到可控制 组合器电路（16）使得组合器电路（16）以上下跟踪模式将第一和第二数模转换电路（14a，b）确定的第一和第二组合器输出信号提供给第二比较器输入端 并且在相对电平检测模式中将与第一和第二组合器输出信号的平均值对应的第三组合器输出信号提供给第二比较器输入。 控制电路（18）具有耦合到比较器（12）的输出端的输入端，控制电路（18）控制第一数模转换电路（14a）向感测信号向上变化的一个方向向上跟踪 在向上跟踪模式中，并且通过第二数模转换电路（14b）控制向上跟踪模式中感测信号的向下变化的一个方向向下跟踪。