公开(公告)号：US20060002292A1

公开(公告)日：2006-01-05

申请号：US10903437

申请日：2004-07-30

申请人： Rong-Feng Chang ,  Eric Lin ,  Craig Barrack

发明人： Rong-Feng Chang ,  Eric Lin ,  Craig Barrack

IPC分类号： H04L1/00

CPC分类号： H04L12/462 ,  H04L43/10 ,  H04L45/02 ,  H04L45/22 ,  H04L45/28

摘要： A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.

摘要翻译： 提供了基于硬件的故障转移方案，实现快速的端到端恢复。 硬件逻辑周期性地生成，发送，接收和处理从通信网络的一端发送到另一端的心跳信息包，然后返回。 如果沿着传输路径遇到通信网络节点或通信链路故障，则硬件逻辑快速地将传送到预先建立的备份传输路径的受影响的业务交换，通常在微秒内。 优点来源于端对端的快速故障转移，从而能够持续提供所提供的通信服务，从而提高通信网络的弹性和/或可用性。

公开(公告)号：US07760726B2

公开(公告)日：2010-07-20

申请号：US12327919

申请日：2008-12-04

申请人： Craig Barrack ,  Yeong Wang ,  Rong-Feng Chang

发明人： Craig Barrack ,  Yeong Wang ,  Rong-Feng Chang

IPC分类号： H04L12/56

CPC分类号： H04L49/352 ,  H04L49/103 ,  H04L49/109 ,  H04L49/90

摘要： A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.

摘要翻译： 介绍了一种双芯片/单芯片开关架构和一种在交换环境中访问DDR SDRAM存储器的方法。 双芯片/单芯片架构包括单芯片上的内部存储器存储块，双倍数据速率同步动态随机存取存储器（DDR SDRAM）的外部存储器存储接口，外部存储器管理器和分组数据 传输引擎在内部存储器存储器和外部DDR SDRAM存储器之间影响数据包数据传输。 分组数据传输引擎作为适应层来操作，以解决与采用适当的：寻址方案，粒度大小，存储器传输突发大小，访问定时等相关的问题。分组数据传输引擎包括最少数量的双模式操作模块，例如： 队列管理器，以及自适应接收和发送块。 该方法涉及一种分组数据传输规程，用于解决在采用DDR SDRAM时引起的随机存储器访问延迟，使用预测库切换来隐藏随机接入延迟，分组长度相关变量存储器写突发长度以最小化库切换，以及执行存储器读写操作 在相应的读写窗口。 优点来源于采用双模式逻辑降低的数据量以及DDR SDRAM带宽利用效率实现的节省空间的双芯片/单芯片开关节点架构。

公开(公告)号：US07486688B2

公开(公告)日：2009-02-03

申请号：US10812141

申请日：2004-03-29

申请人： Craig Barrack ,  Yeong Wang ,  Rong-Feng Chang

发明人： Craig Barrack ,  Yeong Wang ,  Rong-Feng Chang

IPC分类号： H04L12/28

CPC分类号： H04L49/352 ,  H04L49/103 ,  H04L49/109 ,  H04L49/90

摘要： A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.

摘要翻译： 介绍了一种双芯片/单芯片开关架构和一种在交换环境中访问DDR SDRAM存储器的方法。 双芯片/单芯片架构包括单芯片上的内部存储器存储块，双倍数据速率同步动态随机存取存储器（DDR SDRAM）的外部存储器存储接口，外部存储器管理器和分组数据 传输引擎在内部存储器存储器和外部DDR SDRAM存储器之间影响数据包数据传输。 分组数据传输引擎作为适应层来操作，以解决与采用适当的：寻址方案，粒度大小，存储器传输突发大小，访问定时等相关的问题。分组数据传输引擎包括最少数量的双模式操作模块，例如： 队列管理器，以及自适应接收和发送块。 该方法涉及一种分组数据传输规程，用于解决在采用DDR SDRAM时引起的随机存储器访问延迟，使用预测库切换来隐藏随机接入延迟，分组长度相关变量存储器写突发长度以最小化库切换，以及执行存储器读写操作 在相应的读写窗口。 优点来源于采用双模式逻辑降低的数据量以及DDR SDRAM带宽利用效率实现的节省空间的双芯片/单芯片开关节点架构。

公开(公告)号：US20060023640A1

公开(公告)日：2006-02-02

申请号：US10901873

申请日：2004-07-29

申请人： Rong-Feng Chang ,  Mike Twu ,  Craig Barrack ,  Allen Yu

发明人： Rong-Feng Chang ,  Mike Twu ,  Craig Barrack ,  Allen Yu

IPC分类号： H04L12/28

CPC分类号： H04L41/0803 ,  H04L49/555 ,  H04L49/557 ,  H04L49/65

摘要： A methods and apparatus for remote management of switching network nodes in a stack via in-band messaging are presented. Switching nodes in the stack default to reserved switching node identifiers and stacking ports default to a blocking state upon startup, restart, and reset. Each command frame received via a blocking state is forwarded to a command engine at each switching node and is acknowledged with the current switching node identifier. Each acknowledgement frame bearing the reserved network node identifier triggers configuration of the acknowledging switching node. Switching nodes and the management processor track interrupt state vectors regarding events. An interrupt acknowledgement process is employed to track raised interrupts. Configuration of switching node is performed via command frames transmitted by the management processor and destined to a command engine associated with the switching node. Services provided by the management processor are requested via control frames destined to the switching node to which the management processor is attached and destined to the management port thereof. The advantages are derived from engineered switching node deployments wherein an appropriate number of management processors, less than the number of switching nodes in the stack, are employed to provide services to corresponding switching nodes in the stack, based on processing, control, and configuration bandwidth requirements. The in-band configuration and control of the switching nodes in the stack reduce deployment, configuration, management, and maintenance overheads.

摘要翻译： 提出了一种用于通过带内消息传递来对堆叠中的交换网络节点进行远程管理的方法和装置。 堆叠中的交换节点默认为保留的交换节点标识符，堆叠端口在启动，重新启动和重置时默认为阻塞状态。 经由阻塞状态接收的每个命令帧被转发到每个交换节点处的命令引擎，并且用当前交换节点标识符进行确认。 具有保留网络节点标识符的每个确认帧触发确认交换节点的配置。 交换节点和管理处理器跟踪关于事件的中断状态向量。 采用中断确认过程来跟踪提升的中断。 交换节点的配置通过由管理处理器发送并发往与交换节点相关联的命令引擎的命令帧来执行。 由管理处理器提供的服务通过去往管理处理器所连接的转发节点的控制帧被请求并发往其管理端口。 优点来源于工程交换节点部署，其中基于处理，控制和配置带宽，采用小于堆叠中的交换节点数量的适当数量的管理处理器来向堆栈中的相应交换节点提供服务 要求。 堆叠中的交换节点的带内配置和控制可以减少部署，配置，管理和维护开销。

公开(公告)号：US20050213571A1

公开(公告)日：2005-09-29

申请号：US10812141

申请日：2004-03-29

申请人： Craig Barrack ,  Yeong Wang ,  Rong-Feng Chang

发明人： Craig Barrack ,  Yeong Wang ,  Rong-Feng Chang

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L49/352 ,  H04L49/103 ,  H04L49/109 ,  H04L49/90

摘要： A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.

摘要翻译： 介绍了一种双芯片/单芯片开关架构和一种在交换环境中访问DDR SDRAM存储器的方法。 双芯片/单芯片架构包括单芯片上的内部存储器存储块，双倍数据速率同步动态随机存取存储器（DDR SDRAM）的外部存储器存储接口，外部存储器管理器和分组数据 传输引擎在内部存储器存储器和外部DDR SDRAM存储器之间影响数据包数据传输。 分组数据传输引擎作为适应层来操作，以解决与采用适当的：寻址方案，粒度大小，存储器传输突发大小，访问定时等相关的问题。分组数据传输引擎包括最少数量的双模式操作模块，例如： 队列管理器，以及自适应接收和发送块。 该方法涉及一种分组数据传输规程，用于解决在采用DDR SDRAM时引起的随机存储器访问延迟，使用预测库切换来隐藏随机接入延迟，分组长度相关变量存储器写突发长度以最小化库切换，以及执行存储器读写操作 在相应的读写窗口。 优点来源于采用双模式逻辑降低的数据量以及DDR SDRAM带宽利用效率实现的节省空间的双芯片/单芯片开关节点架构。

公开(公告)号：US07974272B2

公开(公告)日：2011-07-05

申请号：US10901873

申请日：2004-07-29

申请人： Rong-Feng Chang ,  Mike Twu ,  Craig Barrack ,  Allen Yu

发明人： Rong-Feng Chang ,  Mike Twu ,  Craig Barrack ,  Allen Yu

IPC分类号： H04Q11/00 ,  H04L12/56

CPC分类号： H04L41/0803 ,  H04L49/555 ,  H04L49/557 ,  H04L49/65

摘要： A methods and apparatus for remote management of switching network nodes in a stack via in-band messaging are presented. Switching nodes in the stack default to reserved switching node identifiers and stacking ports default to a blocking state upon startup, restart, and reset. Each command frame received via a blocking state is forwarded to a command engine at each switching node and is acknowledged with the current switching node identifier. Each acknowledgement frame bearing the reserved network node identifier triggers configuration of the acknowledging switching node. Switching nodes and the management processor track interrupt state vectors regarding events. An interrupt acknowledgement process is employed to track raised interrupts. Configuration of switching node is performed via command frames transmitted by the management processor and destined to a command engine associated with the switching node. Services provided by the management processor are requested via control frames destined to the switching node to which the management processor is attached and destined to the management port thereof. The advantages are derived from engineered switching node deployments wherein an appropriate number of management processors, less than the number of switching nodes in the stack, are employed to provide services to corresponding switching nodes in the stack, based on processing, control, and configuration bandwidth requirements. The in-band configuration and control of the switching nodes in the stack reduce deployment, configuration, management, and maintenance overheads.

摘要翻译： 提出了一种用于通过带内消息传递来对堆叠中的交换网络节点进行远程管理的方法和装置。 堆叠中的交换节点默认为保留的交换节点标识符，堆叠端口在启动，重新启动和重置时默认为阻塞状态。 经由阻塞状态接收的每个命令帧被转发到每个交换节点处的命令引擎，并且用当前交换节点标识符进行确认。 具有保留网络节点标识符的每个确认帧触发确认交换节点的配置。 交换节点和管理处理器跟踪关于事件的中断状态向量。 采用中断确认过程来跟踪提升的中断。 交换节点的配置通过由管理处理器发送并发往与交换节点相关联的命令引擎的命令帧来执行。 由管理处理器提供的服务通过去往管理处理器所连接的转发节点的控制帧被请求并发往其管理端口。 优点来源于工程交换节点部署，其中基于处理，控制和配置带宽，采用小于堆叠中的交换节点数量的适当数量的管理处理器来向堆栈中的相应交换节点提供服务 要求。 堆叠中的交换节点的带内配置和控制可以减少部署，配置，管理和维护开销。

公开(公告)号：US20090086733A1

公开(公告)日：2009-04-02

申请号：US12327919

申请日：2008-12-04

申请人： Craig Barrack ,  Yeong Wang ,  Rong-Feng Chang

发明人： Craig Barrack ,  Yeong Wang ,  Rong-Feng Chang

IPC分类号： H04L12/56

CPC分类号： H04L49/352 ,  H04L49/103 ,  H04L49/109 ,  H04L49/90

摘要： A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.

摘要翻译： 介绍了一种双芯片/单芯片开关架构和一种在交换环境中访问DDR SDRAM存储器的方法。 双芯片/单芯片架构包括单芯片上的内部存储器存储块，双倍数据速率同步动态随机存取存储器（DDR SDRAM）的外部存储器存储接口，外部存储器管理器和分组数据 传输引擎在内部存储器存储器和外部DDR SDRAM存储器之间影响数据包数据传输。 分组数据传输引擎作为适应层来操作，以解决与采用适当的：寻址方案，粒度大小，存储器传输突发大小，访问定时等相关的问题。分组数据传输引擎包括最少数量的双模式操作模块，例如： 队列管理器，以及自适应接收和发送块。 该方法涉及一种分组数据传输规程，用于解决在采用DDR SDRAM时引起的随机存储器访问延迟，使用预测库切换来隐藏随机接入延迟，分组长度相关变量存储器写突发长度以最小化库切换，以及执行存储器读写操作 在相应的读写窗口。 优点来源于采用双模式逻辑降低的数据量以及DDR SDRAM带宽利用效率实现的节省空间的双芯片/单芯片开关节点架构。

公开(公告)号：US06954424B2

公开(公告)日：2005-10-11

申请号：US09794184

申请日：2001-02-26

申请人： Craig I. Barrack ,  Brian Yang ,  John Lam ,  Rong-Feng Chang

发明人： Craig I. Barrack ,  Brian Yang ,  John Lam ,  Rong-Feng Chang

IPC分类号： H04L12/56 ,  H04J1/16

CPC分类号： H04L47/10 ,  H04L47/39 ,  H04L49/25 ,  H04L49/30 ,  H04L49/505

摘要： A credit-based pacing scheme for heterogeneous speed frame forwarding. A control logic controls the transmission of data between a source device and a destination device in accordance with a handshaking protocol. Pacing logic paces the transmission of the data from the source device to the destination device to prevent congestion in the switching fabric. A credit scheme is used to arbitrate among multiple pacing modules per device, each forwarding data at a different rate.

摘要翻译： 用于异构速度帧转发的基于信用的起搏方案。 控制逻辑根据握手协议来控制源设备和目的地设备之间的数据传输。 起搏逻辑将数据从源设备传输到目标设备，以防止交换结构中的拥塞。 信用方案用于在每个设备的多个起搏模块之间进行仲裁，每个转发数据以不同的速率转发。

公开(公告)号：US5367523A

公开(公告)日：1994-11-22

申请号：US112737

申请日：1993-08-26

申请人： Rong-Feng Chang ,  John E. Drake, Jr. ,  Levent Gun ,  Lap T. Huynh

发明人： Rong-Feng Chang ,  John E. Drake, Jr. ,  Levent Gun ,  Lap T. Huynh

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04J3/22

CPC分类号： H04L47/10 ,  H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5632

摘要： An end-to-end, closed loop flow and congestion control system for packet communications networks exchanges rate request and rate response messages between data senders and receivers to allow the sender to adjust the data rate to avoid congestion and to control the data flow. Requests and responses are piggy-backed on data packets and result in changes in the input data rate in a direction to optimize data throughput. GREEN, YELLOW and RED operating modes are defined to increase data input, reduce data input and reduce data input drastically, respectively. Incremental changes in data input are altered non-linearly to change more quickly when further away from the optimum operating point than when closer to the optimum operating point.

摘要翻译： 分组通信网络的端到端闭环流和拥塞控制系统在数据发送者和接收者之间交换速率请求和速率响应消息，以允许发送者调整数据速率以避免拥塞并控制数据流。 请求和响应对数据包进行捎带，并导致输入数据速率的变化，以便优化数据吞吐量。 绿色，黄色和红色操作模式被定义为分别增加数据输入，减少数据输入和减少数据输入。 数据输入的增量变化被非线性地改变，以便在距离最佳工作点更远时比在更接近最佳工作点时更快地改变。