公开(公告)号：US5990519A

公开(公告)日：1999-11-23

申请号：US200891

申请日：1998-11-27

Applicant: Shiang Huang-Lu ,  Tien-Hao Tang ,  Kuan-Yu Fu

Inventor： Shiang Huang-Lu ,  Tien-Hao Tang ,  Kuan-Yu Fu

IPC: H01L23/60 ,  H01L23/62

CPC classification number: H01L23/60 ,  H01L2924/0002

Abstract: A spike electrostatic discharge (ESD) cavity structure includes an etching stop layer including, for example, polysilicon or metal material. The etching stop layer is used as the etching stop to form an opening in the dielectric layer, inside of which a number of discharging layer pairs are formed. The opening exposes the end portions of the discharge layer pairs. The opening is a cavity and can be vacuumed or filled with air.

Abstract translation: 尖峰静电放电（ESD）腔结构包括例如包括多晶硅或金属材料的蚀刻停止层。 蚀刻停止层用作蚀刻停止层以在电介质层中形成开口，其内部形成有多个放电层对。 开口露出放电层对的端部。 开口是一个空腔，可以被抽真空或充满空气。

公开(公告)号：US5864157A

公开(公告)日：1999-01-26

申请号：US12960

申请日：1998-01-26

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H01L29/423 ,  H01L29/788

CPC classification number: H01L29/7883 ,  H01L29/42324

Abstract: A flash memory device that can be erased and programmed electrically, the flash memory device includes an array of transistor memory cell units each has N-doped source and drain regions formed in the device substrate. An N-doped buried channel is formed in the device substrate located between the source and drain regions. A P-doped floating gate is further formed substantially above the buried channel, and a control gate is formed on top of the floating gate. The different doping pattern in the buried channel and the floating gate establishes an increased programming bias voltage for the flash device when operating in its programming mode so that programming speed of the device is faster than conventional. The device can also be fabricated in smaller dimensions with improved reliability.

Abstract translation: 闪存器件可以被擦除和电气编程，闪速存储器件包括晶体管存储单元阵列阵列，每个晶体管存储单元单元在器件衬底中形成有N掺杂的源极和漏极区。 在位于源极和漏极区之间的器件衬底中形成N掺杂掩埋沟道。 进一步在掩埋沟道的上方形成P掺杂的浮置栅极，并且在浮置栅极的顶部上形成控制栅极。 当在其编程模式下工作时，掩埋沟道和浮置栅极中的不同掺杂图案为闪存器件提供增加的编程偏置电压，使得器件的编程速度比常规更快。 该装置还可以以更小的尺寸制造，具有更高的可靠性。

公开(公告)号：US06368911B2

公开(公告)日：2002-04-09

申请号：US09179311

申请日：1998-10-27

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H01L218242

CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/78

Abstract: A method of manufacturing buried gates by performing two trench-forming operations. The method includes forming a first trench in a substrate, and then forming a dielectric layer over the substrate and the interior surface of the first trench. Next, conductive material is deposited into the first trench. Thereafter, second trenches are formed crossing the first trench alternately, wherein the second trenches has a depth greater than the depth of the first trench. Subsequently, insulation material is deposited into the second trenches simultaneously forming buried gates and isolation structures. Floating and control gates are then formed over the buried gates. A similar method can be used to form buried conductive layer by omitting the formation of the dielectric layer.

Abstract translation: 通过进行两个沟槽形成操作来制造掩埋栅极的方法。 该方法包括在衬底中形成第一沟槽，然后在衬底和第一沟槽的内表面上形成电介质层。 接下来，导电材料沉积到第一沟槽中。 此后，交替地形成与第一沟槽交叉的第二沟槽，其中第二沟槽的深度大于第一沟槽的深度。 随后，绝缘材料沉积到第二沟槽中，同时形成掩埋栅极和隔离结构。 然后在掩埋门上形成浮动和控制门。 可以通过省略电介质层的形成来使用类似的方法来形成掩埋的导电层。

公开(公告)号：US06350626B1

公开(公告)日：2002-02-26

申请号：US09410393

申请日：1999-10-01

Applicant: Donald Cheng ,  Kuan-Yu Fu

Inventor： Donald Cheng ,  Kuan-Yu Fu

IPC: H01L2166

CPC classification number: G01R31/2642

Abstract: A method of testing EM lifetime has following steps. First, a pre-characterizing step is performed to obtain parameters such as TC(the critical temperature,), Wc (the critical line width), QGB(the activation energy of grain boundary diffusion) and QL(the activation energy of lattice diffusion) of a metal prior to the use of the test methodology for a new technology. Next, whether a real line width (W) of the metal is narrower or wider than WC is determined. For the narrower line widths, the diffusion mechanism is dominated by the Lattice diffusion only and corresponds to single activation energy (QL). A WLR isothermal test with a relatively high temperature, such as 400° C., can be implemented to reduce the test time to as short as a few seconds. The EM lifetime (t50) under normal operating condition can be directly obtained by conversion from Ttest to TC by using QL.

Abstract translation: 测试EM寿命的方法有以下步骤。 首先，进行预特征化步骤以获得诸如TC（临界温度），Wc（临界线宽度），QGB（晶界扩散的活化能）和QL（晶格扩散的活化能） 在使用新技术的测试方法之前，必须使用金属。 接下来，确定金属的实线宽度（W）是否比WC窄或宽。 对于较窄的线宽，扩散机制仅由晶格扩散控制，对应于单个激活能（QL）。 可以实现具有相对较高温度（例如400℃）的WLR等温试验，以将测试时间缩短至几秒钟。 正常工作条件下的EM寿命（t50）可以通过使用QL从Ttest转换为TC直接获得。

公开(公告)号：US06289291B1

公开(公告)日：2001-09-11

申请号：US09213198

申请日：1998-12-17

Applicant: Mu-Chun Wang ,  Kuan-Yu Fu

Inventor： Mu-Chun Wang ,  Kuan-Yu Fu

IPC: G01N3700

CPC classification number: H01L22/20 ,  G01N2033/0095

Abstract: A statistical method of monitoring the yield of a gate oxide layer. A voltage is applied to first test keys and second test keys to build curves showing relationship between failure distribution and charge density, wherein each of the first test keys has a first oxide area and each of the second test keys has a second oxide area. A yield of the first test keys and a yield of the second test keys up to a charge density can be obtained. The yields of the first test keys and the second test keys have a relationship as an equation of area. To obtain a yield of small test keys, a yield and area of large test keys are imported into an equation. According to operating the equation, the yield of a small gate oxide is obtained.

Abstract translation: 监测栅极氧化层的产率的统计方法。 对第一测试键和第二测试键施加电压以构建示出故障分布和电荷密度之间的关系的曲线，其中每个第一测试键具有第一氧化物区域，并且每个第二测试键具有第二氧化物区域。 可以获得第一测试键的产量和达到电荷密度的第二测试键的产量。 第一测试键和第二测试键的产量具有作为面积方程的关系。 为了获得小的测试键的产量，将大的测试键的产量和面积导入到等式中。 根据该方程式，得到小栅极氧化物的产率。

公开(公告)号：US06269315B1

公开(公告)日：2001-07-31

申请号：US09232202

申请日：1999-01-14

Applicant: Kuan-Yu Fu ,  Chuan H. Liu ,  Donald Cheng ,  Sheng-Hsing Yang ,  Mu-Chun Wang

Inventor： Kuan-Yu Fu ,  Chuan H. Liu ,  Donald Cheng ,  Sheng-Hsing Yang ,  Mu-Chun Wang

IPC: G01R2702

CPC classification number: G01R31/129

Abstract: A method for testing the reliability of a dielectric thin film. An exponential current ramp test is performed with a delay time to test the dielectric thin film. An exponential current ramp charge-to-breakdown distribution, which is represented by cumulative distribution failure percentage, is obtained. An exponential current ramp charge-to-breakdown at a cumulative distribution failure percentage is calculated. An exponential current ramp constant and a constant current stress constant at the cumulative distribution failure percentage are calculated. A constant current stress charge-to-breakdown at the cumulative distribution failure percentage is calculated by using a specified current density and the constant current stress constant at the cumulative distribution failure percentage. The constant current stress charge-to-breakdown at the cumulative distribution failure percentage is compared to a specified constant current stress charge-to-breakdown to determine the reliability of the dielectric thin film.

Abstract translation: 一种用于测试电介质薄膜可靠性的方法。 以延迟时间进行指数电流斜坡测试来测试电介质薄膜。 获得由累积分布失效百分比表示的指数电流斜坡电荷到击穿分布。 计算累积分布失败百分比下的指数电流斜坡电荷分解。 计算累积分布失效百分比下的指数电流斜坡常数和恒定电流应力常数。 通过使用规定的电流密度和累积分布失效百分比下的恒定电流应力常数来计算累积分布失效百分比下的恒定电流应力电荷分解。 将累积分布失效百分比下的恒定电流应力电荷击穿与特定的恒定电流应力电荷分解进行比较，以确定电介质薄膜的可靠性。

公开(公告)号：US06184122B2

公开(公告)日：2001-02-06

申请号：US09213197

申请日：1998-12-17

Applicant: Kuan-Yu Fu ,  Shiang Huang-Lu

Inventor： Kuan-Yu Fu ,  Shiang Huang-Lu

IPC: H01L214763

CPC classification number: H01L23/5225 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preventing horizontal and vertical crosstalk between conductive layers forms a dummy conductive layer between conductive layers and between conductive lines within a dielectric layer. The dummy conductive layer does not connect with conductive layers or conductive lines. Because the dummy conductive layer has a shielding effect for conductive layers, the method can reduce the horizontal and vertical crosstalk between conductive layers.

Abstract translation: 用于防止导电层之间的水平和垂直串扰的方法在导电层之间和介电层内的导电线之间形成虚设导电层。 虚拟导电层不与导电层或导电线连接。 由于虚拟导电层对导电层具有屏蔽效果，所以该方法可以减小导电层之间的水平和垂直串扰。

公开(公告)号：US6063674A

公开(公告)日：2000-05-16

申请号：US181119

申请日：1998-10-28

Applicant: Sheng-Hsing Yang ,  Kuan-Yu Fu

Inventor： Sheng-Hsing Yang ,  Kuan-Yu Fu

IPC: H01L21/336

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/0847 ,  H01L29/42368

Abstract: A method for forming high voltage devices is provided. A P-type semiconductor substrate is provided. An oxide layer is formed on the P-type semiconductor substrate. A first P-well and a second P-well are formed in the P-type semiconductor substrate. A first N-well is formed in the second p-well and a second N-well is formed in the first P-well. A field oxide layer on the second N-well and a gate oxide layer are formed on the P-type substrate. A polysilicon layer is formed and defined as a gate on the gate oxide layer across a portion of the field oxide layer and aportion of the first N-well. A source region is formed in the first N-well and a drain region is formed in the second N-well. A P.sup.+ -type doped region is formed between the substrate and the source region across a part of the first N-well within the second P-well.

Abstract translation: 提供了形成高压器件的方法。 提供了P型半导体衬底。 在P型半导体基板上形成氧化物层。 在P型半导体衬底中形成第一P阱和第二P阱。 在第二p阱中形成第一N阱，在第一P阱中形成第二N阱。 在P型衬底上形成第二N阱上的场氧化物层和栅氧化层。 形成多晶硅层，并且在栅极氧化物层上形成栅极，跨过场氧化物层的一部分和第一N阱的离子化。 在第一N阱中形成源极区，在第二N阱中形成漏极区。 在第二P阱中的第一N阱的一部分之间，在衬底和源区之间形成P +型掺杂区。

公开(公告)号：US6052269A

公开(公告)日：2000-04-18

申请号：US235023

申请日：1999-01-21

Applicant: Tien-Hao Tang ,  Shiang Huang-Lu ,  Kuan-Yu Fu

Inventor： Tien-Hao Tang ,  Shiang Huang-Lu ,  Kuan-Yu Fu

IPC: H01L23/60 ,  H01T4/08 ,  H02H3/22

CPC classification number: H01L23/60 ,  H01T4/08 ,  H01L2924/0002

Abstract: A protection circuit using point discharge suitable for use in an integrated circuit, protects circuit from damage by electrostatic discharge. The integrated circuit at least comprises an input/output port, a high voltage line, and a low voltage line. The protection circuit has point discharge structures at two ends of the input/output ports, respectively corresponding to the point discharge structures of the high and low voltage lines, and is suitable for use in all semiconductor fabricating processes.

Abstract translation: 一种适用于集成电路的点放电保护电路，可保护电路免受静电放电损坏。 集成电路至少包括输入/​​输出端口，高压线路和低压线路。 保护电路在输入/输出端口的两端具有分别对应于高压线和低压线的点放电结构的点放电结构，并且适用于所有半导体制造工艺。

公开(公告)号：US6033959A

公开(公告)日：2000-03-07

申请号：US59548

申请日：1998-04-13

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7834 ,  H01L21/28114 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/42376 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66787

Abstract: A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures. There is a multiple T-shaped gate with a first part and a second part, wherein the first part is formed between two trenches on the substrate and the second part is formed in the trenches of the active region. There is a source/drain region with a shallow doped region and a deep doped region. The multiple T-shaped gate increases the channel width of the MOSFET device and decreases the short channel effect of the high integrity ICs.

Abstract translation: 制造具有多个T形栅极的MOSFET器件的方法具有以下步骤。 提供了具有有源区和非有源区的衬底，其中有源区具有多个沟槽，并且非有源区具有多个浅沟槽隔离结构。 在沟槽中形成薄的绝缘层和导电层。 导电层被定义为形成栅极。 器件植入第一个离子。 然后，通过使用掩模将器件进一步注入第二离子，其中掩模暴露有源区的沟槽，并且掩模的开口比沟槽更宽。 MOSFET器件至少具有以下结构。 存在具有有源区和非有源区的衬底，其中有源区具有多个沟槽，而非有源区具有多个浅沟槽隔离结构。 存在具有第一部分和第二部分的多个T形门，其中第一部分形成在衬底上的两个沟槽之间，并且第二部分形成在有源区域的沟槽中。 存在具有浅掺杂区域和深掺杂区域的源极/漏极区域。 多个T形栅极增加了MOSFET器件的沟道宽度，并降低了高完整性IC的短沟道效应。