公开(公告)号：US20220320140A1

公开(公告)日：2022-10-06

申请号：US17223050

申请日：2021-04-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan Lung

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L21/285 ,  H01L21/764 ,  H01L29/06 ,  H01L29/45

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

公开(公告)号：US20190386213A1

公开(公告)日：2019-12-19

申请号：US16009901

申请日：2018-06-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01L45/00 ,  H01L27/24

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point. The memory cells in the stacks include confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers.

公开(公告)号：US20190304985A1

公开(公告)日：2019-10-03

申请号：US15938695

申请日：2018-03-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792

Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a stack of conductive strips and an opening through the stack exposing sidewalls of conductive strips on first and second sides of the opening. Some of the conductive strips in the stack are configured as word lines. Data storage structures are disposed on the sidewalls of the stack. A vertical channel film is disposed vertically in contact with the data storage structures. The vertical channel film is connected at a proximal end to an upper channel pad over the stack, and at a distal end to a lower channel pad disposed in a lower level of the opening. The upper and lower channel pads may comprise an epitaxial semiconductor and be thicker than the vertical channel film disposed on the sidewalls of the stack.

公开(公告)号：US20240244819A1

公开(公告)日：2024-07-18

申请号：US18188612

申请日：2023-03-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Feng-Min LEE

IPC: H10B12/00

CPC classification number: H10B12/20

Abstract: A semiconductor structure is provided. The semiconductor structure has a device defining region. The device defining region includes a first portion and a second portion separated from each other. The semiconductor structure includes a stack. The stack includes first conductive layers and first dielectric layers disposed alternately. The stack has an opening through the stack in the device defining region. The semiconductor structure further includes a second conductive layer, a first conductive pillar, a third conductive layer, a second conductive pillar, and a third conductive pillar. The second conductive layer is disposed along a sidewall of the opening. The first conductive pillar is disposed in the opening in the first portion. The third conductive layer is disposed in the opening along an edge of the second portion. The second conductive pillar and the third conductive pillar are disposed in the second portion and separated from each other.

公开(公告)号：US20240090238A1

公开(公告)日：2024-03-14

申请号：US18519230

申请日：2023-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Erh-Kun LAI ,  Dai-Ying LEE ,  Yu-Hsuan LIN ,  Po-Hao TSENG ,  Ming-Hsiu LEE

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/845 ,  H10B61/22 ,  H10B63/34 ,  H10N50/01 ,  H10N70/066

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

公开(公告)号：US20230301117A1

公开(公告)日：2023-09-21

申请号：US17698110

申请日：2022-03-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG ,  Chih-Hsiang YANG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1675

Abstract: A memory device includes a substrate, a first conductive stripe disposed on the substrate and extending along a first direction, a second conductive stripe disposed on the first conductive stripe, a first pillar element and a spacer. The second conductive stripe extends along a second direction intersected with the first direction. A thickness of the second conductive stripe is greater than a thickness of the first conductive stripe, and the second conductive stripe is an integral structure. The first pillar element is disposed at an intersection between the first conductive stripe and the second conductive stripe, and extends from a top surface of the first conductive stripe to a bottom surface of the second conductive stripe along a third direction intersected with the first direction and the second direction. The first pillar element includes a switching layer and a memory layer corresponding to a first level.

公开(公告)号：US20230118088A1

公开(公告)日：2023-04-20

申请号：US17504599

申请日：2021-10-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a bottom dielectric layer continuously disposed on the substrate. The semiconductor structure further includes a plurality of stacks disposed on the bottom dielectric layer. Each of the stacks includes gate electrodes and semiconductor layers disposed alternately. The semiconductor structure further includes a plurality of source/drain structures disposed on the bottom dielectric layer and between the stacks. The semiconductor structure further includes a plurality of conductors landed on highest gate electrodes of the stacks.

公开(公告)号：US20220336145A1

公开(公告)日：2022-10-20

申请号：US17234891

申请日：2021-04-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01F27/32 ,  H01F27/28 ,  H01F41/12

Abstract: An inductor structure and a manufacturing method for the same are provided. The inductor structure includes conductive layers and conductive elements. The conductive layers overlap in a vertical direction. Each of the conductive elements is coupled between two conductive layers of the conductive layers.

公开(公告)号：US20210217767A1

公开(公告)日：2021-07-15

申请号：US16742113

申请日：2020-01-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A memory device includes a stack structure, a memory element, a channel element, and a semiconductor layer. The stack structure includes a source layer, an insulating layer and gate electrode layers. The insulating layer is on the source layer. The gate electrode layers are on the insulating layer. The memory element is on electrode sidewall surfaces of the gate electrode layers. Memory cells are defined in the memory element between the channel element and the gate electrode layers. The semiconductor layer is electrically connected between the source layer and the channel element. The semiconductor layer and the source layer have an interface therebetween.
The interface is at a location on an inside of an insulating sidewall surface of the insulating layer with a lateral offset relative to the insulating sidewall surface.

公开(公告)号：US20190355903A1

公开(公告)日：2019-11-21

申请号：US16259746

申请日：2019-01-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsiang-Lan LUNG ,  Erh-Kun LAI ,  Chiao-Wen YEH

IPC: H01L45/00

Abstract: A 3D memory includes a plurality of first access line levels, a plurality of second access line levels and a plurality of memory cell levels, the memory cell levels being disposed between corresponding first access line levels and second access line levels. The first access line levels include a plurality of first access lines extending in a first direction, and a plurality of remnants of a first sacrificial material disposed between the first access lines. The second access line levels include a plurality of second access lines extending in a second direction and a plurality of remnants of a second sacrificial material disposed between the second access lines. The memory cell levels include an array of memory pillars disposed in the cross-points between the first access lines and the second access lines in adjacent first and second access line levels.