公开(公告)号：US20240153869A1

公开(公告)日：2024-05-09

申请号：US18412747

申请日：2024-01-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

公开(公告)号：US20230045495A1

公开(公告)日：2023-02-09

申请号：US17392365

申请日：2021-08-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Erh-Kun LAI ,  Dai-Ying LEE ,  Yu-Hsuan LIN ,  Po-Hao TSENG ,  Ming-Hsiu LEE

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L45/00

Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

公开(公告)号：US20220285385A1

公开(公告)日：2022-09-08

申请号：US17190576

申请日：2021-03-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI

IPC: H01L27/11582 ,  H01L29/06 ,  H01L21/764

Abstract: A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stack disposed on the substrate, wherein the stack includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the upper surface of the substrate along a first direction; a channel layer penetrating the stack along the first direction, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction; and a memory layer disposed between the channel layer and the second conductive layer.

公开(公告)号：US20250089269A1

公开(公告)日：2025-03-13

申请号：US18464332

申请日：2023-09-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG

IPC: H10B63/00 ,  H01L23/522

Abstract: A semiconductor device includes a stack and a plurality of vertical pillar structures disposed in the stack. The stack includes a plurality of insulating layers and a plurality of conductive layers alternately arranged, each of the conductive layers includes a center portion and a plurality of edge portions at edges of the center portion, wherein a resistance of a material of the edge portions is less than a resistance of a material of the center portion. Each of the vertical pillar structures includes a conductive core, a shell electrode on a sidewall of the conductive core, and an ovonic threshold switch (OTS) layer on a sidewall of the shell electrode. A method of forming the semiconductor device is also disclosed.

公开(公告)号：US20240365565A1

公开(公告)日：2024-10-31

申请号：US18306289

申请日：2023-04-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Feng-Min LEE

IPC: H10B63/00 ,  H10B61/00

CPC classification number: H10B63/34 ,  H10B61/22 ,  H10B63/845

Abstract: A memory device and a method for manufacturing the same are provided. The memory device includes drain pillar structures, source pillar structures, memory structures surrounding the drain pillar structures respectively, a channel structure, and a gate structure surrounding the drain pillar structures, the source pillar structures and the channel structure. The channel structure is divided into arc channel parts by the drain pillar structures and the source pillar structures.

公开(公告)号：US20230354602A1

公开(公告)日：2023-11-02

申请号：US17731304

申请日：2022-04-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Feng-Min LEE

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

Abstract: An integrated circuit structure includes a substrate, an interconnect stack, a first memory array, and a source line. The interconnect stack is over the substrate. The first memory array is over the interconnect stack and includes memory elements stacked in a vertical direction each comprising a conductive layer. The first memory array further includes a memory layer electrically connecting to the conductive layers of the memory elements and extending downwardly from a topmost one of the conductive layers to a lowermost one of the conductive layers; and a channel layer extending along a sidewall of the memory layer. The source line is in contact with a top end of the channel layer and laterally extends across the first memory array.

公开(公告)号：US20220302029A1

公开(公告)日：2022-09-22

申请号：US17249837

申请日：2021-03-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H01L21/768

Abstract: A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer comprises a first conductive film. The semiconductor structure includes a landing pad disposed on the first conductive film. The landing pad has a first pad sidewall facing toward the second stair layer, a first lateral gap distance between an upper portion of the first pad sidewall and the second stair layer is smaller than a second lateral gap distance between a lower portion of the first pad sidewall and the second stair layer.

公开(公告)号：US20250089268A1

公开(公告)日：2025-03-13

申请号：US18464326

申请日：2023-09-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Hsiang-Lan LUNG ,  Wei-Chih CHIEN

IPC: H10B63/00 ,  H10N70/00

Abstract: A semiconductor device includes a stack including a plurality of insulating layers and a plurality of word plane conductors alternately arranged, a vertical pillar structure disposed in the stack, and a plurality of outer electrodes. The vertical pillar structure includes a conductive core, an inner electrode on a sidewall of the conductive core, and an ovonic threshold switch (OTS) layer on a sidewall of the inner electrode, in which the inner electrode is disposed between the conductive core and the OTS layer. The outer electrodes are disposed between the OTS layer and the word plane conductors, wherein a resistance of a material of the word plane conductors is less than a resistance of a material of the outer electrodes. A method of forming the semiconductor device is also disclosed.

公开(公告)号：US20240371443A1

公开(公告)日：2024-11-07

申请号：US18310593

申请日：2023-05-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Feng-Min LEE

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: An integrated circuit structure includes a substrate, a first memory string, a source line, and a second memory string. The first memory string is over the substrate and comprises first memory cells stacked in a vertical direction. The source line laterally extends over the first memory string. The second memory string is over the source line and comprises second memory cells stacked in the vertical direction.

公开(公告)号：US20230282511A1

公开(公告)日：2023-09-07

申请号：US18316584

申请日：2023-05-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/48

CPC classification number: H01L21/76816 ,  H01L21/02225 ,  H01L21/02458 ,  H01L21/02472 ,  H01L21/3065 ,  H01L21/486

Abstract: A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer includes a first conductive film. The semiconductor structure includes a first landing pad disposed on the first conductive film. The first landing pad has a first pad sidewall facing toward the second stair layer, and a second pad sidewall opposite to the first pad sidewall. The second pad sidewall includes an inclined sidewall portion.