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公开(公告)号：US20250169385A1
公开(公告)日：2025-05-22
申请号：US18631117
申请日：2024-04-10
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min LEE , Yu-Yu LIN , Po-Hao TSENG , Ming-Hsiu LEE
Abstract: A semiconductor structure includes a gate, a channel structure, a gate insulating layer, a source, and a drain. The channel structure includes a threshold switching material, in which the channel structure includes a layered channel, a columnar channel, or a plurality of nanosheet channels. The gate insulating layer is disposed between the gate and the channel structure. The source is in direct contact with the channel structure. The drain is in direct contact with the channel structure.
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公开(公告)号：US20250123750A1
公开(公告)日：2025-04-17
申请号：US18378960
申请日：2023-10-11
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao TSENG , Ming-Hsiu LEE
IPC: G06F3/06
Abstract: A high-level architecture for 3D-NAND based in-memory search provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. A search word is presented to a 3D-NAND memory along a direction of a bit line of the 3D-NAND memory. Each character of the word comprises a number of digits. Each digit is matched against respective layers of the 3D-NAND memory. Each digit is usable to represent one of a plurality of levels according to a selected encoding. Optionally, various lengths of words are accommodated via serial and/or parallel operations of one or more 3D-NAND memories.
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公开(公告)号：US20230253039A1
公开(公告)日：2023-08-10
申请号：US17842989
申请日：2022-06-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE , Ming-Hsiu LEE
CPC classification number: G11C13/0033 , G11C13/004 , G11C13/0011 , G11C13/0069 , H01L45/085 , H01L45/1266
Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.
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4.发明申请公开(公告)号：US20230075257A1
公开(公告)日：2023-03-09
申请号：US18055855
申请日：2022-11-16
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ming-Hsiu LEE , Po-Hao TSENG
Abstract: A multilevel content addressable memory, a multilevel coding method and a multilevel searching method are provided. The multilevel coding method includes the following steps. A highest decimal value of a multilevel-bit binary data is obtained. A length of a digital string data is set as being the highest decimal value of the multilevel-bit binary data. The multilevel-bit binary data is converted into the digital string data. If a content of the multilevel-bit binary data is an exact value, a number of an indicating bit in the digital string data is the exact value.
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5.发明申请公开(公告)号：US20210224041A1
公开(公告)日：2021-07-22
申请号：US16807194
申请日：2020-03-03
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao TSENG , Ming-Hsiu LEE , Yu-Hsuan LIN
Abstract: A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.
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Patent Agency Ranking
公开(公告)号：US20250087268A1
公开(公告)日：2025-03-13
申请号：US18367075
申请日：2023-09-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao TSENG , Ming-Hsiu LEE
Abstract: A non-volatile 3D memory search architecture provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. The architecture uses two word lines per unit of information of the searches and two memory devices per unit of stored feature to search against. The architecture uses respective bit lines of the non-volatile 3D memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the non-volatile 3D memory array are usable to store respective data values, e.g., corresponding to elements to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. The architecture has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.
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公开(公告)号：US20250022508A1
公开(公告)日：2025-01-16
申请号：US18903041
申请日：2024-10-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE , Ming-Hsiu LEE
Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.
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公开(公告)号：US20240194229A1
公开(公告)日：2024-06-13
申请号：US18064303
申请日：2022-12-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yun-Yuan WANG , Cheng-Hsien LU , Po-Hao TSENG , Ming-Hsiu LEE
CPC classification number: G11C7/1069 , G11C7/14 , G11C8/08
Abstract: The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.
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公开(公告)号：US20240012567A1
公开(公告)日：2024-01-11
申请号：US18069255
申请日：2022-12-21
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao TSENG , Feng-Min LEE , Tian-Cih BO , Ming-Hsiu LEE
IPC: G06F3/06
CPC classification number: G06F3/0614 , G06F3/0659 , G06F3/0673
Abstract: A memory device is provided. The memory device includes channel layers, word lines, memory layers disposed between the channel layers and the word lines, and memory cells defined at cross-points of the channel layers and the word lines. The memory device is configured for performing a first operation for m times and a second operation for n times, and m is equal to or larger than n. In the first operation, a first electric field is produced in a portion of the memory layers. The word lines are configured for producing a second electric field in the second operation in the portion of the memory layers, and a field direction of the second electric field is different from a field direction of the first electric field.
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公开(公告)号：US20230045495A1
公开(公告)日：2023-02-09
申请号：US17392365
申请日：2021-08-03
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min LEE , Erh-Kun LAI , Dai-Ying LEE , Yu-Hsuan LIN , Po-Hao TSENG , Ming-Hsiu LEE
Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.
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