公开(公告)号：US11222693B2

公开(公告)日：2022-01-11

申请号：US17035885

申请日：2020-09-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun Li ,  Wei-Chen Wang

IPC: G11C16/34 ,  G11C11/56 ,  G06F12/02 ,  G11C16/10 ,  G11C16/16

Abstract: A data management method for a memory is provided. The memory includes memory pages. Each of the memory pages includes memory cells. A data update command corresponding to a logical address is received. The logical address maps to a physical address of a target memory page before receiving the data update command. First and second reading voltages are applied to obtain at least a first and a second target memory cell to be sanitized in the target memory page of the memory pages, a first programming voltage is applied to change the logical state of the first target memory cell to a logical state with a higher threshold voltage, and a second programming voltage is applied to change the logical state of the second target memory cell to a logical state with a higher threshold voltage. The first programming voltage is different from the second programming voltage.

公开(公告)号：US11042308B2

公开(公告)日：2021-06-22

申请号：US16742811

申请日：2020-01-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chen Wang ,  Ping-Hsien Lin ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G06F16/901 ,  G06F12/10

Abstract: A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.

公开(公告)号：US20210158160A1

公开(公告)日：2021-05-27

申请号：US17096575

申请日：2020-11-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chen Wang ,  Shu-Yin Ho ,  Chien-Chung Ho ,  Yuan-Hao Chang

IPC: G06N3/08 ,  G06N3/04 ,  G06F3/06

Abstract: An operation method of an artificial neural network is provided. The operation method includes: dividing input information into a plurality of sub-input information, and expanding kernel information to generate expanded kernel information; performing a Fast Fourier Transform (FFT) on the sub-input information and the expanded kernel information to respectively generate a plurality of frequency domain sub-input information and frequency domain expanded kernel information; respectively performing a multiplying operation on the frequency domain expanded kernel information and the frequency domain sub-input information to respectively generate a plurality of sub-feature maps; and performing an inverse FFT on the sub-feature maps to provide a plurality of converted sub-feature maps for executing a feature extraction operation of the artificial neural network.