公开(公告)号：US11606063B2

公开(公告)日：2023-03-14

申请号：US17695863

申请日：2022-03-16

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

公开(公告)号：US20220209715A1

公开(公告)日：2022-06-30

申请号：US17695863

申请日：2022-03-16

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

公开(公告)号：US11309835B2

公开(公告)日：2022-04-19

申请号：US17306960

申请日：2021-05-04

Applicant: MEDIATEK INC.

Inventor： Sen-You Liu ,  Chien-Wei Chen ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

公开(公告)号：US11722139B2

公开(公告)日：2023-08-08

申请号：US17575646

申请日：2022-01-14

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Chao-Ching Hung

IPC: H03L7/02 ,  H03L7/099 ,  H03L7/00 ,  H03L1/02

CPC classification number: H03L7/02 ,  H03L1/02 ,  H03L7/00 ,  H03L7/0995

Abstract: A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

公开(公告)号：US20220399897A1

公开(公告)日：2022-12-15

申请号：US17575646

申请日：2022-01-14

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Chao-Ching Hung

IPC: H03L7/099

Abstract: A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

公开(公告)号：US20220209714A1

公开(公告)日：2022-06-30

申请号：US17693454

申请日：2022-03-14

Applicant: MEDIATEK INC.

Inventor： Sen-You Liu ,  Chien-Wei Chen ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

公开(公告)号：US11342884B2

公开(公告)日：2022-05-24

申请号：US17306959

申请日：2021-05-04

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

公开(公告)号：US20210091720A1

公开(公告)日：2021-03-25

申请号：US17026275

申请日：2020-09-20

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Po-Chun Huang

IPC: H03B5/06 ,  H03B5/36 ,  G01R25/00

Abstract: A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.