公开(公告)号：US09385744B2

公开(公告)日：2016-07-05

申请号：US14016246

申请日：2013-09-03

Applicant: MEDIATEK INC.

Inventor： Yun-Shiang Shu

IPC: H03M3/00

CPC classification number: H03M3/322 ,  H03M3/388 ,  H03M3/458

Abstract: A delta-sigma analog-to-digital converter (ΔΣ ADC) has a delta-sigma modulator, a decimation filter and an error suppression circuit. The delta-sigma modulator receives an analog input, and converts the analog input into a first digital output. The decimation filter is coupled to the delta-sigma modulator, and generates a second digital output according to the first digital output. The error suppression circuit is coupled to the decimation filter, and receives an error input and injects an error output into the second digital output according to the error input.

Abstract translation: Δ-Σ模数转换器（＆Dgr＆amp;＆amp; ADC）具有Δ-Σ调制器，抽取滤波器和误差抑制电路。 Δ-Σ调制器接收模拟输入，并将模拟输入转换为第一数字输出。 抽取滤波器耦合到Δ-Σ调制器，并根据第一数字输出产生第二数字输出。 误差抑制电路耦合到抽取滤波器，并接收误差输入，并根据误差输入将误差输出注入到第二数字输出端。

公开(公告)号：US10911059B2

公开(公告)日：2021-02-02

申请号：US16809581

申请日：2020-03-05

Applicant: MEDIATEK INC.

Inventor： Wei-Hsiang Huang ,  Yun-Shiang Shu ,  Su-Hao Wu

IPC: H03M1/06 ,  A61B5/04 ,  A61B5/00

Abstract: A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.

公开(公告)号：US20180183461A1

公开(公告)日：2018-06-28

申请号：US15830000

申请日：2017-12-04

Applicant: MEDIATEK INC.

Inventor： Qiang Zhou ,  Hua Wang ,  Yun-Shiang Shu ,  Bao-Chi Peng

IPC: H03M7/30 ,  A61B5/00

CPC classification number: H03M7/3088 ,  A61B5/0002 ,  A61B5/0024 ,  A61B5/021 ,  A61B5/0261 ,  A61B5/0402 ,  A61B5/6802 ,  A61B5/7232 ,  A61B2503/10 ,  H03M7/3062

Abstract: An electronic device has a transmit circuit and a processing circuit. The processing circuit outputs a first portion of compressive sensing (CS) samples corresponding to a signal segment to another electronic device via the transmit circuit, and selectively outputs a second portion of the CS samples corresponding to the signal segment to another electronic device via the transmit circuit according to a response of another electronic device. In this way, a balance between the compression ratio and the reconstruction quality/speed can be achieved. Moreover, the signal reconstruction performed at the processing circuit may employ a multi-resolution/multi-scale reconstruction scheme to achieve a balance between the dictionary size and the reconstruction quality/speed, and/or may employ a multi-stage reconstruction scheme to achieve a balance between the reconstruction algorithm control setting and the reconstruction quality/speed. In addition, dictionary weighting, online dictionary update, and/or point constraints may be used to improve the reconstruction quality.

公开(公告)号：US20170077937A1

公开(公告)日：2017-03-16

申请号：US15246580

申请日：2016-08-25

Applicant: MEDIATEK Inc.

Inventor： Yun-Shiang Shu

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/066 ,  H03M1/001 ,  H03M1/0673 ,  H03M1/145 ,  H03M1/68 ,  H03M3/338 ,  H03M3/344

Abstract: The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit couple to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit combines the digital injection value and one of the following: the second digital value and a related value obtained according to the second analog value.

Abstract translation: 本发明提供了一种用于在具有失配误差整形的模拟域和数字域之间转换的系统，包括DAC，耦合到DAC的第一注入电路和耦合到DAC的第二注入电路。 DAC响应于第一数字值产生第一模拟值，并响应于第二数字值产生第二模拟值。 当DAC产生第二模拟值时，第一注入电路使得能够将模拟注入值注入到第二模拟值，其中模拟注入值从由第一数字值的位的子集形成的数字注入值转换。 第二注入电路组合数字注入值和以下之一：第二数字值和根据第二模拟值获得的相关值。

公开(公告)号：US09236855B2

公开(公告)日：2016-01-12

申请号：US14504787

申请日：2014-10-02

Applicant: MediaTek Inc.

Inventor： Yun-Shiang Shu

IPC: H03F3/45 ,  H03K5/24

CPC classification number: H03K5/2481 ,  H03F3/45 ,  H03F3/45071 ,  H03F3/45179 ,  H03F3/45197 ,  H03F2203/45424 ,  H03F2203/45466 ,  H03F2203/45482 ,  H03F2203/45492 ,  H03K5/2472 ,  H03K5/249

Abstract: A comparator has a differential pair circuit and a current control circuit. The differential pair circuit has first and second comparator transistors, and is arranged to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset. The current control circuit is coupled in series with the differential pair circuit, and configured to provide unequal abilities of drawing currents for the first and second comparator transistors. An amplifier circuit is also disclosed, having a differential pair circuit, a current control circuit, an amplification circuit and a reset circuit.

Abstract translation: 比较器具有差分对电路和电流控制电路。 差分对电路具有第一和第二比较器晶体管，并且被布置为根据时钟信号比较第一输入和第二输入，以产生指示第一和第二输入的差是否超过内部偏移的结果。 电流控制电路与差分对电路串联耦合，并且被配置为提供对第一和第二比较器晶体管的拉电流的不相等的能力。 还公开了具有差分对电路，电流控制电路，放大电路和复位电路的放大器电路。

公开(公告)号：US20140077984A1

公开(公告)日：2014-03-20

申请号：US14022182

申请日：2013-09-09

Applicant: MEDIATEK INC.

Inventor： Yun-Shiang Shu

IPC: H03M3/00

CPC classification number: H03M3/30 ,  H03M3/37 ,  H03M3/458

Abstract: A delta-sigma modulator has a delta-sigma modulation loop and a plurality of excess loop delay (ELD) adjustment circuits. The delta-sigma modulation loop converts an analog input into a digital output. The ELD adjustment circuits perform different ELD adjustments according to the digital output for jointly adjusting an ELD of the delta-sigma modulation loop. Besides, a delta-sigma modulation method includes at least the following steps: converting an analog input into a digital output through a delta-sigma modulation loop; and employing different ELD adjustment schemes for jointly adjusting an ELD of the delta-sigma modulation loop according to the digital output.

Abstract translation: Δ-Σ调制器具有Δ-Σ调制环路和多个过剩环路延迟（ELD）调节电路。 Δ-Σ调制环路将模拟输入转换为数字输出。 ELD调整电路根据数字输出执行不同的ELD调整，以共同调整Δ-Σ调制环路的ELD。 此外，Δ-Σ调制方法至少包括以下步骤：通过Δ-Σ调制环将模拟输入转换成数字输出; 并采用不同的ELD调整方案，以根据数字输出共同调整Δ-Σ调制环路的ELD。