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公开(公告)号:US20230367358A1
公开(公告)日:2023-11-16
申请号:US17867779
申请日:2022-07-19
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Natan Manevich , Dotan David Levi , Wojciech Wasko , Ariel Almog , Bar Shapira
Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.
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公开(公告)号:US12028155B2
公开(公告)日:2024-07-02
申请号:US17534776
申请日:2021-11-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Bar Shapira , Ariel Almog , Dotan David Levi , Natan Manevich , Thomas Kernen , Liron Mula
IPC: H04J3/06
CPC classification number: H04J3/0638
Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
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公开(公告)号:US20230236624A1
公开(公告)日:2023-07-27
申请号:US17582058
申请日:2022-01-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dotan David Levi , Wojciech Wasko , Eitan Zahavi , Natan Manevich , Bar Shapira
CPC classification number: G06F1/14 , H04J3/0697 , H04J3/0682 , H04J3/0661 , H04J3/0679 , G06F1/12
Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.
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公开(公告)号:US20230163869A1
公开(公告)日:2023-05-25
申请号:US17534776
申请日:2021-11-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Bar Shapira , Ariel Almog , Dotan David Levi , Natan Manevich , Thomas Kernen , Liron Mula
IPC: H04J3/06
CPC classification number: H04J3/0638
Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
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公开(公告)号:US20220191275A1
公开(公告)日:2022-06-16
申请号:US17120313
申请日:2020-12-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dotan David Levi , Avraham Ganor , Arnon Sattinger , Natan Manevich , Reuven Kogan , Artiom Tsur , Ariel Almog , Bar Shapira
Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.
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