公开(公告)号：US12148498B2

公开(公告)日：2024-11-19

申请号：US17959191

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Antonino Caprì ,  Daniele Balluchi ,  Massimiliano Patriarca

IPC: G11C11/406 ,  G11C11/4093 ,  G11C29/52

Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

公开(公告)号：US20230062130A1

公开(公告)日：2023-03-02

申请号：US17895041

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Simone Corbetta ,  Antonino Caprì ,  Emanuele Confalonieri

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to access request management using sub-commands. Access requests received from a host system can be managed using a respective set of sub-commands corresponding to each access request and whose status can be tracked. Tracking how far access requests are processed at a fine granularity (of sub-commands) can provide efficient management of the access requests that can reduce a gap latency in processing multiple access requests.

公开(公告)号：US20220374150A1

公开(公告)日：2022-11-24

申请号：US17748644

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Antonino Caprì ,  Emanuele Confalonieri ,  Simone Corbetta ,  Michela Spagnolo

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to an adjustable timer component are described. A memory device includes, a memory controller coupled to the memory device comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, responsive to receiving the request, store in a cache an active timer entry corresponding to a particular first address, generate a timer corresponding to an active timer entry and the particular first address, and monitor the timer to determine when the timer expires. Responsive to the expiration of the timer, dequeue the timer entry and invalidate the timer entry stored in the cache. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine if the cache includes an active timer entry corresponding to the particular second address.