公开(公告)号：US20230170016A1

公开(公告)日：2023-06-01

申请号：US18096072

申请日：2023-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0038

Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

公开(公告)号：US11442091B2

公开(公告)日：2022-09-13

申请号：US16877710

申请日：2020-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu

IPC: G01R27/26 ,  G11C16/08 ,  G11C16/04 ,  G01R27/08

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to determine capacitance and/or resistance values of an access line in response to applying a reference current to the access line, wherein the access line is connected to control gates of memory cells of the array of memory cells.

公开(公告)号：US20210366558A1

公开(公告)日：2021-11-25

申请号：US17443370

申请日：2021-07-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhengyi Zhang ,  Dan Xu ,  Tomoko Ogura Iwasaki

IPC: G11C16/28 ,  G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/30

Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.