-
公开(公告)号：US12101932B2
公开(公告)日：2024-09-24
申请号：US17450729
申请日：2021-10-13
CPC分类号： H10B41/41 , B81B7/02 , G11C7/1012 , G11C16/24 , H10B41/20 , H10B43/20 , H10B43/40 , B81B2201/07
摘要： A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.
-
公开(公告)号：US20230078401A1
公开(公告)日：2023-03-16
申请号：US17989168
申请日：2022-11-17
发明人： Jun Xu , Violante Moschiano , Erwin E. Yu
摘要： A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.
-
公开(公告)号：US11532367B2
公开(公告)日：2022-12-20
申请号：US17115357
申请日：2020-12-08
发明人： Jun Xu , Violante Moschiano , Erwin E. Yu
摘要： A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.
-
4.发明申请公开(公告)号：US20210201993A1
公开(公告)日：2021-07-01
申请号：US17011018
申请日：2020-09-03
发明人： Dan Xu , Jun Xu , Erwin E. Yu , Paolo Tessariol , Tomoko Ogura Iwasaki
IPC分类号： G11C13/00
摘要： Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.
-
公开(公告)号：US20210202009A1
公开(公告)日：2021-07-01
申请号：US16991836
申请日：2020-08-12
发明人： Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
摘要： A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.
-
6.发明公开公开(公告)号：US20240203508A1
公开(公告)日：2024-06-20
申请号：US18589730
申请日：2024-02-28
发明人： Chulbum Kim , Brian Kwon , Erwin E. Yu , Kitae Park , Taehyun Kim
CPC分类号： G11C16/14 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/225 , G11C16/32
摘要： A memory device includes a memory array comprising memory cells and control logic operatively coupled with the memory array. The control logic causes, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array. The control logic tracks a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erased. The control logic causes, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation. The control logic, in response to the number of suspend commands satisfying a threshold criterion, alerts the processing device to terminate sending suspend commands.
-
公开(公告)号：US20240170075A1
公开(公告)日：2024-05-23
申请号：US18387217
申请日：2023-11-06
发明人： Kwang Ho Kim , Erwin E. Yu
摘要： Entry of a memory device into a standby mode is determined. During the standby mode of the memory device, a first bias voltage level is caused to be applied to a sense amplifier latch of a sense amplifier of a page buffer circuit of the memory device. During the standby mode, a second bias voltage level is caused to be applied to a set of data latches of the sense amplifier of the page buffer circuit of the memory device, wherein the second bias voltage level is different from the first bias voltage level.
-
公开(公告)号：US11862257B2
公开(公告)日：2024-01-02
申请号：US17989168
申请日：2022-11-17
发明人： Jun Xu , Violante Moschiano , Erwin E. Yu
CPC分类号： G11C16/3454 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3404
摘要： A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.
-
公开(公告)号：US20230047662A1
公开(公告)日：2023-02-16
申请号：US17445045
申请日：2021-08-13
IPC分类号： H01L27/11556 , H01L27/11582 , G11C5/06 , G11C5/02 , H01L23/538 , H01L27/092
摘要： A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.
-
公开(公告)号：US20220404408A1
公开(公告)日：2022-12-22
申请号：US17894227
申请日：2022-08-24
发明人： Dan Xu , Jun Xu , Erwin E. Yu
摘要： Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.
-
-
-
-
-
-
-
-
-
搜索结果
33 条记录 (耗时 0.02 秒)
