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公开(公告)号：US12276686B2
公开(公告)日：2025-04-15
申请号：US17894227
申请日：2022-08-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dan Xu , Jun Xu , Erwin E. Yu
Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.
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公开(公告)号：US20240428862A1
公开(公告)日：2024-12-26
申请号：US18748679
申请日：2024-06-20
Applicant: Micron Technology, Inc.
Inventor： Taehyun Kim , Brian Kwon , Dong Kyo Shim , Kwang Ho Kim , Erwin E. Yu , Fulvio Rori
Abstract: Control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. During the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. During the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.
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公开(公告)号：US12101932B2
公开(公告)日：2024-09-24
申请号：US17450729
申请日：2021-10-13
Applicant: Micron Technology, Inc.
Inventor： Erwin E. Yu , Surendranath C. Eruvuru , Yoshiaki Fukuzumi , Tomoko Ogura Iwasaki
CPC classification number: H10B41/41 , B81B7/02 , G11C7/1012 , G11C16/24 , H10B41/20 , H10B43/20 , H10B43/40 , B81B2201/07
Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号：US20230078401A1
公开(公告)日：2023-03-16
申请号：US17989168
申请日：2022-11-17
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Violante Moschiano , Erwin E. Yu
Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.
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公开(公告)号：US11532367B2
公开(公告)日：2022-12-20
申请号：US17115357
申请日：2020-12-08
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Violante Moschiano , Erwin E. Yu
Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20210201993A1
公开(公告)日：2021-07-01
申请号：US17011018
申请日：2020-09-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dan Xu , Jun Xu , Erwin E. Yu , Paolo Tessariol , Tomoko Ogura Iwasaki
IPC: G11C13/00
Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.
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公开(公告)号：US20250098159A1
公开(公告)日：2025-03-20
申请号：US18969510
申请日：2024-12-05
Applicant: Micron Technology, Inc.
Inventor： Erwin E. Yu , Michele Piccardi , Surendranath C. Eruvuru
IPC: H10B41/27 , B81B1/00 , G11C5/02 , G11C5/06 , H01L23/538 , H01L27/092 , H10B43/27
Abstract: A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.
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公开(公告)号：US20250008727A1
公开(公告)日：2025-01-02
申请号：US18886735
申请日：2024-09-16
Applicant: Micron Technology, Inc.
Inventor： Erwin E. Yu , Surendranath C. Eruvuru , Yoshiaki Fukuzumi , Tomoko Ogura Iwasaki
Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号：US20210202009A1
公开(公告)日：2021-07-01
申请号：US16991836
申请日：2020-08-12
Applicant: Micron Technology, Inc.
Inventor： Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.
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公开(公告)号：US12171096B2
公开(公告)日：2024-12-17
申请号：US17445045
申请日：2021-08-13
Applicant: Micron Technology, Inc.
Inventor： Erwin E. Yu , Michele Piccardi , Surendranath C. Eruvuru
IPC: G11C5/06 , G11C5/02 , H01L23/538 , H01L27/092 , H10B41/27 , H10B43/27 , B81B1/00
Abstract: A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.
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