GRAPHICS RENDER CLOCK THROTTLING AND GATING MECHANISM FOR POWER SAVING
    11.
    发明申请
    GRAPHICS RENDER CLOCK THROTTLING AND GATING MECHANISM FOR POWER SAVING 有权
    图形渲染时钟节流和节能机制

    公开(公告)号:US20110148887A1

    公开(公告)日:2011-06-23

    申请号:US12908308

    申请日:2010-10-20

    IPC分类号: G06T1/00

    CPC分类号: G06T1/00

    摘要: An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.

    摘要翻译: 控制器电路的示例可以包括:策略模块,用于基于处理器功率状态输入生成功率降低策略输出。 还可以基于图形渲染引擎空闲输入来生成功率降低策略输出。 电路还可以包括时钟屏蔽单元,以基于功率降低策略输出将时钟屏蔽配置应用于图形渲染时钟中继。

    Graphics render clock throttling and gating mechanism for power saving
    12.
    发明授权
    Graphics render clock throttling and gating mechanism for power saving 有权
    图形渲染时钟节流和门控机构节省电能

    公开(公告)号:US08780121B2

    公开(公告)日:2014-07-15

    申请号:US12908308

    申请日:2010-10-20

    CPC分类号: G06T1/00

    摘要: An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.

    摘要翻译: 控制器电路的示例可以包括:策略模块,用于基于处理器功率状态输入生成功率降低策略输出。 还可以基于图形渲染引擎空闲输入来生成功率降低策略输出。 电路还可以包括时钟屏蔽单元,以基于功率降低策略输出将时钟屏蔽配置应用于图形渲染时钟中继。