公开(公告)号：US07069525B2

公开(公告)日：2006-06-27

申请号：US10623249

申请日：2003-07-18

申请人： Manjul Bhushan ,  Mark B. Ketchen

发明人： Manjul Bhushan ,  Mark B. Ketchen

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A set of ring oscillators is formed within a predetermined distance of each other. Each ring oscillator includes a number of coupled stages. The stages for a first given ring oscillator include an inverter having one or more first MOS devices having a first gate length. The stages for a second given ring oscillator include one or more second MOS devices having a second designed gate length. The stages for a third given ring oscillator comprise one or more third MOS devices having a third designed gate length. The second and third designed gate lengths are different and one of the second and third designed gate lengths is approximately equal to the first designed gate length. Performance is measured by using one of more of the given ring oscillators. The set of ring oscillators is used to determine one or more additional characteristics of MOS devices in the ring oscillators.

摘要翻译： 一组环形振荡器形成在彼此的预定距离内。 每个环形振荡器包括多个耦合级。 第一给定环形振荡器的级包括具有一个或多个具有第一栅极长度的第一MOS器件的反相器。 第二给定环形振荡器的级包括具有第二设计栅极长度的一个或多个第二MOS器件。 第三给定环形振荡器的级包括具有第三设计栅极长度的一个或多个第三MOS器件。 第二和第三设计的栅极长度是不同的，并且第二和第三设计的栅极长度之一近似等于第一设计栅极长度。 通过使用更多的给定环形振荡器中的一个来测量性能。 该组环形振荡器用于确定环形振荡器中的MOS器件的一个或多个附加特性。

公开(公告)号：US06960926B2

公开(公告)日：2005-11-01

申请号：US10178883

申请日：2002-06-24

申请人： Carl J. Anderson ,  Manjul Bhushan ,  Mark B. Ketchen

发明人： Carl J. Anderson ,  Manjul Bhushan ,  Mark B. Ketchen

IPC分类号： G01R31/30 ,  G01R31/26

CPC分类号： G01R31/3016

摘要： A method of characterizing a circuit comprises the steps of measuring a first delay associated with the circuit when the circuit is substantially unloaded; measuring a second delay associated with the circuit when the circuit is loaded by a predetermined impedance; determining a difference between the second delay and the first delay, the delay difference corresponding to a switching impedance associated with the circuit; and determining a characterization parameter of the circuit, the characterization parameter being a function of at least the switching impedance associated with the circuit. The methodologies of the present invention are directed primarily to individually evaluating pullup and pulldown delays with substantial precision (e.g., sub-picosecond) for a representative set of circuits in the presence of an arbitrary switching history.

摘要翻译： 一种表征电路的方法包括以下步骤：当电路基本上卸载时测量与电路相关联的第一延迟; 当所述电路以预定阻抗加载时，测量与所述电路相关联的第二延迟; 确定所述第二延迟和所述第一延迟之间的差异，所述延迟差对应于与所述电路相关联的开关阻抗; 以及确定所述电路的表征参数，所述表征参数是至少与所述电路相关联的开关阻抗的函数。 本发明的方法主要针对在存在任意切换历史的情况下，针对代表性的一组电路单独地估计上拉和下拉延迟的实质精度（例如，亚皮秒）。

公开(公告)号：US08310269B2

公开(公告)日：2012-11-13

申请号：US12544730

申请日：2009-08-20

申请人： Manjul Bhushan ,  Mark B. Ketchen

发明人： Manjul Bhushan ,  Mark B. Ketchen

IPC分类号： G01R31/26 ,  G01R31/3187

CPC分类号： G01R31/2621 ,  G01R31/3008

摘要： A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.

摘要翻译： 一种用于确定被测集成电路（IC）的泄漏的测试系统，包括与IC相同的芯片上形成的测试电路，该测试电路还具有脉冲发生器，该脉冲发生器被配置成以多个产生IC的高速输入信号 有选择地可编程占空比和频率，所述IC由独立于所述脉冲发生器供电的第二电源的第一电源供电; 以及电流测量装置，其被配置为响应于多个可编程占空比和频率的高速输入信号来测量处于静止状态的通过IC的泄漏电流和通过IC的处于主动切换状态的电流，并且其中 测试电路仅使用相对于芯片的外部低速输入和输出信号。

公开(公告)号：US20110043243A1

公开(公告)日：2011-02-24

申请号：US12544730

申请日：2009-08-20

申请人： Manjul Bhushan ,  Mark B. Ketchen

发明人： Manjul Bhushan ,  Mark B. Ketchen

IPC分类号： G01R31/26 ,  G01R31/02

CPC分类号： G01R31/2621 ,  G01R31/3008

摘要： A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.

摘要翻译： 一种用于确定被测集成电路（IC）的泄漏的测试系统，包括与IC相同的芯片上形成的测试电路，该测试电路还具有脉冲发生器，该脉冲发生器被配置成以多个产生IC的高速输入信号 有选择地可编程占空比和频率，所述IC由独立于所述脉冲发生器供电的第二电源的第一电源供电; 以及电流测量装置，其被配置为响应于多个可编程占空比和频率的高速输入信号来测量处于静止状态的通过IC的泄漏电流和通过IC的处于主动切换状态的电流，并且其中 测试电路仅使用相对于芯片的外部低速输入和输出信号。

公开(公告)号：US20110043215A1

公开(公告)日：2011-02-24

申请号：US12544750

申请日：2009-08-20

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

IPC分类号： G01R31/02

CPC分类号： G01R31/31725 ,  G01R31/3016

摘要： A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each comprising two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.

摘要翻译： 用于集成电路装置的测试结构包括一个或多个实验，其被选择性地配置为接收一个或多个高速输入信号作为其输入并从其输出至少一个高速输出信号，所述一个或多个实验各自包括两个或多个 多个逻辑门被配置为确定各个电路装置的差分延迟特性，其精度水平以皮秒级小于1皮秒; 并且其中所述一组或多组实验在所述集成电路装置中的金属布线（M1）的第一级处被布置并且是完全可测试的。

公开(公告)号：US20090271134A1

公开(公告)日：2009-10-29

申请号：US12110639

申请日：2008-04-28

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

IPC分类号： G01R29/00

CPC分类号： G01R31/31707 ,  G01R31/3016 ,  G01R31/31708 ,  H03K5/04

摘要： Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.

摘要翻译： 提供了用于集成电路装置中的切换历史时间常数的在线测量的技术。 一系列脉冲被发射到延迟链的第一级中，该延迟链包括多个串联连接的延迟级，其长度大于该系列脉冲中的至少初始脉冲的衰减长度，使得至少初始 一系列脉冲之一不出现在延迟链的第二阶段。 确定在延迟链的第二阶段发射一系列脉冲中的初始脉冲之一和至少一个脉冲串的出现之间的时间量。 切换历史时间常数被计算为至少部分地基于至少一个脉冲遍历的次数的数量，所确定的时间量以及该系列脉冲中的至少初始脉冲的衰减长度的函数 集成电路装置的切换历史。

公开(公告)号：US07342406B2

公开(公告)日：2008-03-11

申请号：US11297730

申请日：2005-12-08

申请人： Manjul Bhushan ,  Karen M. G. V. Gettings ,  Wilfried E. Haensch ,  Brian L. Ji ,  Mark B. Ketchen

发明人： Manjul Bhushan ,  Karen M. G. V. Gettings ,  Wilfried E. Haensch ,  Brian L. Ji ,  Mark B. Ketchen

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of measuring variability of integrated circuit components is provided. A specified parameter of at least one first array configuration comprising a plurality of the integrated circuit components without specified internal connections between the integrated circuit components is measured. The specified parameter of at least one second array configuration comprising a plurality of the integrated circuit components nominally identical to those of the first array configuration with specified internal connections between the integrated circuit components is also measured. A variation coefficient is determined for the integrated circuit components based on the measured specified parameter of the at least one first array configuration and the at least one second array configuration.

摘要翻译： 提供了一种测量集成电路部件的可变性的方法。 测量包括集成电路部件之间没有规定内部连接的多个集成电路部件的至少一个第一阵列配置的指定参数。 还测量包括与集成电路部件之间具有规定的内部连接的第一阵列配置的名义上相同的多个集成电路部件的至少一个第二阵列配置的指定参数。 基于所测量的至少一个第一阵列配置和至少一个第二阵列配置的指定参数，为集成电路组件确定变化系数。

公开(公告)号：US07295057B2

公开(公告)日：2007-11-13

申请号：US11037612

申请日：2005-01-18

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Chandrasekharan Kothandaraman ,  Edward P. Maciejewski

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Chandrasekharan Kothandaraman ,  Edward P. Maciejewski

IPC分类号： H01H37/76

CPC分类号： G01R31/31853 ,  G01R31/30 ,  G01R31/3004

摘要： An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

摘要翻译： 提供一种具有至少一个能够被熔断以便提供熔丝电流 - 电压特性测量的熔断器的集成电路器件。 集成电路装置还提供与熔丝相关联的至少一个脉冲发生电路，并且能够产生脉冲以通过一个或多个DC输入信号来熔断熔丝。

公开(公告)号：US09075109B2

公开(公告)日：2015-07-07

申请号：US13410851

申请日：2012-03-02

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

IPC分类号： G01R31/00 ,  G01R31/317 ,  G01R31/30

CPC分类号： G01R31/31725 ,  G01R31/3016

摘要： A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.

公开(公告)号：US08723528B2

公开(公告)日：2014-05-13

申请号：US13104544

申请日：2011-05-10

申请人： Mark B. Ketchen ,  Manjul Bhushan

发明人： Mark B. Ketchen ,  Manjul Bhushan

IPC分类号： G01R31/02

CPC分类号： G01R31/2884

摘要： A structure and method is provided for testing a 2-dimensional array of electrical devices, such as a 2-dimensional array in the first metal level (M1) of an electronic structure. The method for testing the 2-dimensional array provides a parallel test approach. The test structure provides a plurality of test pad structures to implement the parallel test approach. The test pad structures may include field effect transistors.

摘要翻译： 提供了一种用于测试诸如电子结构的第一金属级（M1）中的二维阵列的电气装置的二维阵列的结构和方法。 用于测试二维阵列的方法提供了一种并行测试方法。 测试结构提供了多个测试焊盘结构来实现并行测试方法。 测试焊盘结构可以包括场效应晶体管。