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1.发明授权公开(公告)号：US07595654B2
公开(公告)日：2009-09-29
申请号：US12041388
申请日：2008-03-03
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m×n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration of integrated circuit components comprising an array of integrated circuit components nominally identical to those of the first array configuration, with specified internal connections between integrated circuit components. A variation coefficient is determined for the integrated circuit components based on a measured specified parameter of the first array configuration and the second array configuration.
摘要翻译： 提供一种集成电路器件，其包括至少一个集成电路部件的第一阵列结构，该集成电路部件包括一组FET，该集成电路阵列在集成电路部件之间没有规定的内部连接，其中m大于2。 集成电路装置还包括集成电路部件的至少一个第二阵列配置，其包括与第一阵列配置的名义上相同的集成电路组件的阵列，以及集成电路部件之间的指定的内部连接。 基于第一阵列配置和第二阵列配置的测量的指定参数来确定集成电路组件的变化系数。
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2.发明授权公开(公告)号：US07342406B2
公开(公告)日：2008-03-11
申请号：US11297730
申请日：2005-12-08
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A method of measuring variability of integrated circuit components is provided. A specified parameter of at least one first array configuration comprising a plurality of the integrated circuit components without specified internal connections between the integrated circuit components is measured. The specified parameter of at least one second array configuration comprising a plurality of the integrated circuit components nominally identical to those of the first array configuration with specified internal connections between the integrated circuit components is also measured. A variation coefficient is determined for the integrated circuit components based on the measured specified parameter of the at least one first array configuration and the at least one second array configuration.
摘要翻译： 提供了一种测量集成电路部件的可变性的方法。 测量包括集成电路部件之间没有规定内部连接的多个集成电路部件的至少一个第一阵列配置的指定参数。 还测量包括与集成电路部件之间具有规定的内部连接的第一阵列配置的名义上相同的多个集成电路部件的至少一个第二阵列配置的指定参数。 基于所测量的至少一个第一阵列配置和至少一个第二阵列配置的指定参数，为集成电路组件确定变化系数。
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3.发明申请公开(公告)号：US20080142848A1
公开(公告)日：2008-06-19
申请号：US12041388
申请日：2008-03-03
IPC分类号： H01L27/088
CPC分类号： G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m×n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration of integrated circuit components comprising an array of integrated circuit components nominally identical to those of the first array configuration, with specified internal connections between integrated circuit components. A variation coefficient is determined for the integrated circuit components based on a measured specified parameter of the first array configuration and the second array configuration.
摘要翻译： 提供一种集成电路器件，其包括至少一个集成电路部件的第一阵列结构，该集成电路部件包括一组FET，该集成电路阵列在集成电路部件之间没有规定的内部连接，其中m大于2。 集成电路装置还包括集成电路部件的至少一个第二阵列配置，其包括与第一阵列配置的名义上相同的集成电路组件的阵列，以及集成电路部件之间的指定的内部连接。 基于第一阵列配置和第二阵列配置的测量的指定参数来确定集成电路组件的变化系数。
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4.发明授权Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors 有权嵌入式DRAM集成电路，具有极薄的绝缘体上硅传导晶体管公开(公告)号：US08766410B2
公开(公告)日：2014-07-01
申请号：US13153806
申请日：2011-06-06
申请人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
发明人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
IPC分类号： H01L23/58
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10894
摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。
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公开(公告)号：US08212537B2
公开(公告)日：2012-07-03
申请号：US12508235
申请日：2009-07-23
申请人： Gary D. Carpenter , Wonyoung Kim , Brian L. Ji
发明人： Gary D. Carpenter , Wonyoung Kim , Brian L. Ji
CPC分类号： H02M3/158
摘要： A converter circuit and methods for operating the same. The converter circuit includes a supply voltage, a capacitor, an inductor, and four stacked switching elements. Each switching element is adjustable from a low resistance state to a high resistance state by a control signal. The inductor outputs current to a circuit load. The circuit may be operated in a first mode such that the output is adjustable between the supply voltage and half the supply voltage. Alternatively, in a second mode of operation, the output is adjustable from half the supply voltage to a ground voltage.
摘要翻译： A转换器电路及其操作方法。 转换器电路包括电源电压，电容器，电感器和四个堆叠的开关元件。 每个开关元件可通过控制信号从低电阻状态调节到高电阻状态。 电感将电流输出到电路负载。 电路可以在第一模式下操作，使得输出在电源电压和电源电压的一半之间是可调节的。 或者，在第二操作模式中，输出可从电源电压的一半调整到接地电压。
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公开(公告)号：US08198174B2
公开(公告)日：2012-06-12
申请号：US12536176
申请日：2009-08-05
申请人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
发明人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
IPC分类号： H01L21/44
CPC分类号： H01L23/467 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.
摘要翻译： 提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合 在其接合界面处的垂直堆叠的晶片的晶片。 此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过 一个或多个开口以从芯片堆叠结构移除热量。
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7.发明授权Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors 有权嵌入式DRAM集成电路，具有极薄的绝缘体上硅传导晶体管公开(公告)号：US07985633B2
公开(公告)日：2011-07-26
申请号：US11929943
申请日：2007-10-30
申请人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
发明人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10894
摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。
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公开(公告)号：US20110108900A1
公开(公告)日：2011-05-12
申请号：US12616861
申请日：2009-11-12
申请人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L27/0811 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/94
摘要： A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
摘要翻译： 形成场效应晶体管（FET）电容器的方法包括：形成沟道区; 在沟道区上形成栅叠层; 在所述栅极堆叠的第一侧上形成第一延伸区域，所述第一延伸区域通过以第一角度注入第一掺杂材料形成，使得阴极区域存在于所述栅极叠层的第二侧上; 以及在所述栅极堆叠的第二侧上形成第二延伸区域，所述第二延伸区域通过以第二角度注入第二掺杂材料形成，使得阴极区域存在于所述栅极叠层的第一侧上。
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公开(公告)号：US20110101440A1
公开(公告)日：2011-05-05
申请号：US12612710
申请日：2009-11-05
申请人： Jin Cai , Brian L. Ji , Tak Hung Ning
发明人： Jin Cai , Brian L. Ji , Tak Hung Ning
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823425 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L27/11521 , H01L27/11558 , H01L29/792
摘要： A CMOS device includes a silicon substrate and an electrical insulator formed over the silicon substrate. The device also includes an access pFET formed over the electrical insulator and a first gate stack and a storage pFET formed over the electrical insulator, the storage pFET including a second source region that is co-formed with the first drain region, a second channel region, and a second drain region. The device also includes a second gate stack including a second dielectric layer formed above the second channel region and a floating gate electrode formed above the second gate dielectric layer.
摘要翻译： CMOS器件包括硅衬底和形成在硅衬底上的电绝缘体。 器件还包括形成在电绝缘体上的访问pFET和形成在电绝缘体上的第一栅极堆叠和存储pFET，存储pFET包括与第一漏极区域共同形成的第二源极区域，第二沟道区域 ，和第二漏区。 该器件还包括第二栅极堆叠，其包括形成在第二沟道区上方的第二介电层和形成在第二栅极介电层上方的浮置栅电极。
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公开(公告)号：US20100002481A1
公开(公告)日：2010-01-07
申请号：US12166311
申请日：2008-07-01
申请人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
发明人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
CPC分类号： G11C13/0004 , G11C15/046
摘要： Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.
摘要翻译： 使用相变装置的内容寻址存储装置。 内容可寻址存储器件的一个方面是使用相对较低功率的搜索线访问元件和相对较高功率的字线访问元件。 字线访问元件仅在写入操作期间使用，并且搜索线访问元件仅在搜索操作期间被使用。 字线访问元件电耦合到相变存储器元件的第二端和字线。 搜索线访问元件还电耦合到相变存储元件的第二端和搜索线。 搜索线电耦合到匹配线。 位线电耦合到相变存储元件的第一端。 此外，内容可寻址存储器件中还包括互补的一组存取元件，互补相变存储器元件，互补搜索线和互补位线。
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