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11.发明授权
公开(公告)号：US5553272A
公开(公告)日：1996-09-03
申请号：US316320
申请日：1994-09-30
CPC分类号： G06K9/62 , G06F7/02 , G06K9/00973
摘要： The edit distance between two strings a.sub.1, . . . , a.sub.m and b.sub.1, . . . , b.sub.n is the minimum cost s of a sequence of editing operations (insertions, deletions and substitutions) that convert one string into the other. This invention provides VLSI circuit structure for computing the edit distance between two strings over a given alphabet. The circuit structure can perform approximate string matching for variable edit costs. More importantly, the circuit structure does not place any constraint on the lengths of the strings that can be compared. It makes use of simple basic cells and requires regular nearest-neighbor communication, which makes it suitable for VLSI implementation.
摘要翻译： 两个字符串之间的编辑距离a1，。 。 。 ，am和b1，。 。 。 ，bn是将一个字符串转换为另一个字符串的编辑操作（插入，删除和替换）序列的最小成本。 本发明提供了用于计算给定字母表上的两个字符串之间的编辑距离的VLSI电路结构。 电路结构可以对可变编辑成本执行近似字符串匹配。 更重要的是，电路结构对可以比较的串的长度没有任何约束。 它使用简单的基本单元，并且需要定期的最近邻通信，这使得它适合于VLSI的实现。
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公开(公告)号：US10678907B2
公开(公告)日：2020-06-09
申请号：US15881020
申请日：2018-01-26
摘要： A runtime attack can be detected on a big data system while processes are executed on various computing devices. A behavior profile can be maintained for tasks or processes running on different computing devices. The existence of a call variance in one of the traces for one of the behavior profiles can be determined. A memory variance can also be detected in one of the behavior profiles. A runtime attack has occurred when both the memory variance and the call variance are determined to exist.
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13.发明授权公开(公告)号：US07944230B1
公开(公告)日：2011-05-17
申请号：US12882835
申请日：2010-09-15
IPC分类号： H03K19/003
CPC分类号： H03K19/0033
摘要： The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.
摘要翻译： 本发明包括一种用于防止逻辑单元中软错误传播的电路级系统和方法。 当插入在逻辑单元的输出端时，包括RC微分器和耗尽型MOS电路的根据本发明的辐射干扰电路显着地减少了瞬态毛刺的传播。 辐射干扰电路是一种新颖的晶体管级优化技术，已被用于减少逻辑电路中的软错误。 还介绍了在延迟，功率和面积方面在放大器的逻辑电路中的选择节点上插入辐射干扰信号的方法。
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14.发明授权Conservative logic gate for design of quantum dot cellular automata circuits 有权用于设计量子点单元自动机电路的保守逻辑门公开(公告)号：US07880496B1
公开(公告)日：2011-02-01
申请号：US12702587
申请日：2010-02-09
IPC分类号： H03K19/195 , H03K19/173
CPC分类号： G06N99/002 , B82Y10/00 , Y10S977/94
摘要： A novel conservative gate especially suiting a Quantum Dot Cellular Automata (QCA) majority voter-based design. The input-to-output mapping of the novel conservative QCA (CQCA) gate is: P=A; Q=AB+BC+AC [MV(A,B,C)]; R=A′B+A′C+BC [MV(A′,B,C)], where A, B, C are inputs and P, Q, R are outputs, respectively. A method of transferring information in a quantum-dot cellular automata device is also provided.
摘要翻译： 特别适合量子点细胞自动机（QCA）多数选民设计的小保守门。 新型保守QCA（CQCA）门的输入到输出映射为：P = A; Q = AB + BC + AC [MV（A，B，C）]; R = A'B + A'C + BC [MV（A'，B，C）]，其中A，B，C分别是输入，P，Q，R分别是输出。 还提供了一种在量子点细胞自动机中传送信息的方法。
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15.发明授权公开(公告)号：US07804320B2
公开(公告)日：2010-09-28
申请号：US12484708
申请日：2009-06-15
IPC分类号： H03K19/003
CPC分类号： H03K19/0033
摘要： The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.
摘要翻译： 本发明包括一种用于防止逻辑单元中软错误传播的电路级系统和方法。 当插入在逻辑单元的输出端时，包括RC微分器和耗尽型MOS电路的根据本发明的辐射干扰电路显着地减少了瞬态毛刺的传播。 辐射干扰电路是一种新颖的晶体管级优化技术，已被用于减少逻辑电路中的软错误。 还介绍了在延迟，功率和面积方面在放大器的逻辑电路中的选择节点上插入辐射干扰信号的方法。
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公开(公告)号：US07256608B2
公开(公告)日：2007-08-14
申请号：US11422973
申请日：2006-06-08
IPC分类号： H03K17/16
CPC分类号： H03K19/00361 , H03K17/162 , H03K17/6872 , H03K19/0013 , H03K2217/0036
摘要： An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.
摘要翻译： 描述了根据本发明的有效设计方法，用于减少CMOS电路中的泄漏功率。 根据本发明的方法和装置随着阈值电压的降低而产生更好的泄漏减少，从而有助于进一步降低电源电压并最小化晶体管尺寸。 与其他泄漏控制技术不同，本发明的技术不需要任何控制电路来监测电路的状态。 因此，避免以附加电路消耗的动态功率的形式牺牲获得的泄漏功率降低以控制整体电路状态。
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17.发明授权
公开(公告)号：US5659362A
公开(公告)日：1997-08-19
申请号：US302110
申请日：1994-09-07
申请人： Mario Kovac , Nagarajan Ranganathan
发明人： Mario Kovac , Nagarajan Ranganathan
CPC分类号： G06T9/007
摘要： A fully pipelined VLSI circuit structure for implementing the JPEG baseline image compression standard. The circuit structure exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The entire is designed to be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024.times.1024 color images.
摘要翻译： 完全流水线的VLSI电路结构，用于实现JPEG基线图像压缩标准。 电路结构在最大程度上利用流水线和并行的原理，以获得高速度和吞吐量。 整个设计用于在单个VLSI芯片上实现，以产生大约100MHz的时钟速率，这将允许1024×1024彩色图像的每秒30帧的输入速率。
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公开(公告)号：US5535292A
公开(公告)日：1996-07-09
申请号：US174302
申请日：1993-12-30
CPC分类号： G06K9/6203 , G06K9/6211
摘要： A VLSI structure and method for polygon recognition that identifies an unknown two dimensional contour as corresponding to one or more of a plurality of known two dimensional contours. The VLSI architecture comprises a systolic processing system comprising a plurality of matrix element processing elements (MEPEs), and an array of feasible match processing elements (FMPEs) interconnected with selected MEPEs and with each other in a predetermined configuration. The plurality of MEPEs receive inputs comprising pairs of edge length ratios and corresponding threshold values for consecutive edges of the unknown contour and for each of the known polygon contours. Each MEPE (i) receives edge length ratios and threshold values for a pair of edges of the unknown contour and a known polygon contour, (ii) determines a dissimilarity value for the pair of edges, and (iii) directs this value to a selected FMPE of the array. The dissimilarity value is determined using the absolute differences between respective edge length ratios and threshold values for the pair of edges. The array of FMPEs determines feasible matches between pairs of consecutive edges of the unknown contour and the known polygon contours and delivers outputs related thereto, and a comparator device compares such outputs and delivers a final output which is indicative of the longest number of consecutive edges, above a predetermined minimum, for which feasible matches have occurred between the unknown contour and a known polygon contour.
摘要翻译： 一种用于多边形识别的VLSI结构和方法，其将未知二维轮廓识别为对应于多个已知二维轮廓中的一个或多个。 VLSI架构包括包括多个矩阵元素处理元件（MEPE）的收缩处理系统以及与所选MEPE互连并且以预定配置彼此互连的可行匹配处理元件（FMPE）阵列。 多个MEPE接收包括未知轮廓的连续边缘和已知多边形轮廓中的每一个的边缘长度比对和相应阈值对的输入。 每个MEPE（i）接收未知轮廓的一对边缘和已知多边形轮廓的边缘长度比和阈值，（ii）确定该对边缘的不相似性值，以及（iii）将该值指向所选择的 数组的FMPE。 使用相应边缘长度比和该对边缘的阈值之间的绝对差确定不相似度值。 FMPE阵列确定了未知轮廓和已知多边形轮廓的连续边缘对之间的可行匹配，并且传送与之相关的输出，并且比较器装置比较这样的输出并递送表示最长连续边缘数的最终输出， 高于预定最小值，在未知轮廓和已知多边形轮廓之间发生了可行的匹配。
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