公开(公告)号：US07283926B2

公开(公告)日：2007-10-16

申请号：US11257591

申请日：2005-10-24

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: G01C22/00

CPC classification number: G01S13/74 ,  G01S13/0209 ,  H03K23/54

Abstract: Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.

Abstract translation: 应用于超宽带（UWB）应用的距离估计的计数电路，其中第一计数单元产生不包括零的伪随机数序列，第一记录单元根据序列记录第一序列和第二序列 第一信号和第二信号，并且传送单元根据来自记录单元的第一串联和第二串行生成二进制计数值。

公开(公告)号：US20070093984A1

公开(公告)日：2007-04-26

申请号：US11257591

申请日：2005-10-24

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: G06F15/00

CPC classification number: G01S13/74 ,  G01S13/0209 ,  H03K23/54

Abstract: Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.

公开(公告)号：US06750517B1

公开(公告)日：2004-06-15

申请号：US09706206

申请日：2000-11-06

Applicant: Ming-Dou Ker ,  Mau-Lin Wu

Inventor： Ming-Dou Ker ,  Mau-Lin Wu

IPC: H01L2976

CPC classification number: H01L27/0277 ,  H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layout form ESD-protection MOS transistors include gate electrodes of the ESD-protection MOS transistors being formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. The ESD protection transistors are NMOS and PMOS. The source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes. The wider ends of the gate electrodes straddle the peripheral boundaries of the active region. A modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner transistors.

Abstract translation: ESD保护MOS晶体管的布局形式包括在有源区的外围形成有较宽端的ESD保护MOS晶体管的栅电极，由此晶体管具有改善的导通均匀性。 ESD保护晶体管是NMOS和PMOS。 用于晶体管的源极接触和漏极接触位于有源区的周边的内侧，留下用于栅电极较宽端的空间。 栅电极的较宽端跨越有源区的周边边界。 在高耐压I / O电路中为层叠的NMOS和PMOS器件提供了改进的布局样式，其较宽端仅提供在内部晶体管上。