公开(公告)号：US20090122890A1

公开(公告)日：2009-05-14

申请号：US11937007

申请日：2007-11-08

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: H04L23/02

CPC classification number: H04L27/2649 ,  H04L27/0008 ,  H04L27/0012 ,  H04W52/16

Abstract: An OFDM DCM demodulation method is provided. The OFDM DCM demodulation method mainly includes the following steps. First, calculate a log likelihood of a first demodulation mode. Then calculate a log likelihood of a second demodulation mode. Finally, calculate a demodulation output according to the log likelihoods of the first demodulation mode and the second demodulation mode. The demodulation output may serve as an output of a demodulator of a receiving end of a DCM communication system.

Abstract translation: 提供OFDM DCM解调方法。 OFDM DCM解调方法主要包括以下步骤： 首先，计算第一解调模式的对数似然。 然后计算第二解调模式的对数似然。 最后，根据第一解调模式和第二解调模式的对数似然度来计算解调输出。 解调输出可以用作DCM通信系统的接收端的解调器的输出。

公开(公告)号：US20070089041A1

公开(公告)日：2007-04-19

申请号：US11163398

申请日：2005-10-17

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: H03M13/00

CPC classification number: H04L1/0045 ,  H03M13/09 ,  H04L1/0052 ,  H04L1/0061 ,  H04L1/0072 ,  H04L1/1829

Abstract: A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.

Abstract translation: 用于接收机的重复检测电路包括用于产生帧头信息的CRC值的CRC发生器和耦合到CRC发生器的控制电路。 控制电路具有第一输出，第二输出和控制输入。 当控制输入未设定时，控制电路在第一个输出端输出CRC值。 当控制输入被设置时，控制电路在第二个输出端输出CRC值。 缓冲器具有耦合到控制电路的第一输出的输入。 比较电路具有耦合到缓冲器的输出和耦合到控制电路的第二输出的另一个输入的输入。 比较电路将控制电路的第二输出端的CRC值与存储在缓冲器中的CRC值进行比较，并在检测到匹配时输出重复指示。

公开(公告)号：US20060115024A1

公开(公告)日：2006-06-01

申请号：US10999753

申请日：2004-11-29

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: H04L27/06

CPC classification number: H04L23/02

Abstract: A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying “PAD” to replace “PCD” into “pre-selection” subgroups with “max-and-zero” property, the invention can reduce the implementation cost without performance degradation.

Abstract translation: 提供了快速沃尔什变换（FWT）解调器和方法。 FWT解调器包括用于基于FWT方法接收和变换第一信息以输出第三信息的FWT相关器; 功率近似装置（PAD），用于接收和计算第三信息之一，以分别输出近似功率值。 其中近似功率值被划分为子组。 比较器的第一个单位从每个子组中选择子组 - 最大值。 多个功率计算装置（PCD）用于接收和计算子组最大值之一，以分别输出精确的功率值。 比较器的第二单元用于从每个精确功率值选择最大功率值以输出第二信息。 通过应用“PAD”将“PCD”替换为具有“最大和零”属性的“预选”子组，本发明可以在不降低性能的情况下降低实现成本。

公开(公告)号：US06414532B1

公开(公告)日：2002-07-02

申请号：US09963596

申请日：2001-09-27

Applicant: Hung Der Su ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Mau-Lin Wu

Inventor： Hung Der Su ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Mau-Lin Wu

IPC: H03K508

CPC classification number: H01L27/0266

Abstract: An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.

Abstract translation: 使用驱动电路，ESD保护电路，Vcc / Vss保护电路和钳位电路来提供I / O ESD保护电路。 驱动电路和ESD保护电路各自包括NMOS共源共栅电路。 NMOS晶体管和偏置电阻装置包括Vcc / Vss保护电路。 钳位电路是耦合在保护电路的I / O焊盘和该NMOS晶体管的栅极之间的二极管。 在ESD事件中，二极管导通Vcc / Vss保护电路的NMOS晶体管，因此钳位了两个NMOS共源共栅电路的第一个晶体管。 钳位禁止这些前两个晶体管的栅极通过ESD电压耦合，并在每个共源共栅电路中产生寄生双极晶体管。 寄生双极晶体管在两个NMOS共源共栅电路的P阱的掩埋区域中提供均匀的电流。

公开(公告)号：US20090003385A1

公开(公告)日：2009-01-01

申请号：US11769996

申请日：2007-06-28

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: H04B3/10

CPC classification number: H04L5/0007 ,  H04L25/022 ,  H04L25/0224

Abstract: In a wireless communication method and system, a data/pilot constellation is modulated and generated based on input information bits. Channel estimation (CE) sequence in frequency-domain is off-line generated. The frequency-domain channel estimation sequence is transformed into a time-domain channel estimation sequence by ideal IFFT to avoid IFFT (Inverse Fast Fourier Transform) impact to EVM (Error Vector Magnitude) performance. Off-line resealing the time-domain CE sequence, multiplied by a rescaling coefficient, in time-domain improves EVM performance. Further, the time-domain channel estimation sequence is off-line quantized.

Abstract translation: 在无线通信方法和系统中，基于输入信息比特来调制和生成数据/导频星座。 频域中的信道估计（CE）序列是离线生成的。 通过理想的IFFT将频域信道估计序列变换成时域信道估计序列，以避免对EVM（误差矢量幅度）性能的IFFT（快速傅立叶逆变换）影响。 离线重新密封时域CE序列乘以重新缩放系数，在时域上提高EVM性能。 此外，时域信道估计序列被离线量化。

公开(公告)号：US07369630B2

公开(公告)日：2008-05-06

申请号：US10999753

申请日：2004-11-29

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: H03D1/00 ,  H04L27/06 ,  H04L27/00

CPC classification number: H04L23/02

Abstract: A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying “PAD” to replace “PCD” into “pre-selection” subgroups with “max-and-zero” property, the invention can reduce the implementation cost without performance degradation.

Abstract translation: 提供了快速沃尔什变换（FWT）解调器和方法。 FWT解调器包括用于基于FWT方法接收和变换第一信息以输出第三信息的FWT相关器; 功率近似装置（PAD），用于接收和计算第三信息之一，以分别输出近似功率值。 其中近似功率值被划分为子组。 比较器的第一个单位从每个子组中选择子组 - 最大值。 多个功率计算装置（PCD）用于接收和计算子组最大值之一，以分别输出精确的功率值。 比较器的第二单元用于从每个精确功率值选择最大功率值以输出第二信息。 通过应用“PAD”将“PCD”替换为具有“最大和零”属性的“预选”子组，本发明可以在不降低性能的情况下降低实现成本。

公开(公告)号：US20070286221A1

公开(公告)日：2007-12-13

申请号：US11452791

申请日：2006-06-13

Applicant: Mau-Lin Wu ,  Tung-Hui Lee ,  Chieh-Hua Chen ,  Hsin-Pu Chung ,  Youn-Tai Lee

Inventor： Mau-Lin Wu ,  Tung-Hui Lee ,  Chieh-Hua Chen ,  Hsin-Pu Chung ,  Youn-Tai Lee

IPC: H04L12/56 ,  H04J3/02

CPC classification number: H04L12/403

Abstract: A memory management method and a memory architecture for transmitting ultra-wideband (UWB) prioritized channel access (PCA) frames are provided. The method comprises the steps of assigning a pre-load queue to each of a plurality of access categories for storing UWB PCA frames to be transmitted, and, when one of the access categories gains transmission opportunity (TXOP), assigning a common area queue to that access category for storing UWB PCA frames to be transmitted. Moreover, when a UWB PCA frame in one of the pre-load queues reaches a predetermined size, the access category corresponding to the pre-load queue starts its backoff state machine in order to gain the TXOP.

Abstract translation: 提供了用于发送超宽带（UWB）优先信道接入（PCA）帧的存储器管理方法和存储器架构。 该方法包括以下步骤：将预加载队列分配给用于存储要发送的UWB PCA帧的多个接入类别中的每一个，并且当其中一个接入类别获得传输机会（TXOP）时，将公共区域队列分配给 用于存储要发送的UWB PCA帧的接入类别。 此外，当一个预加载队列中的UWB PCA帧达到预定大小时，对应于预加载队列的访问类别启动其退避状态机，以获得TXOP。

公开(公告)号：US06912109B1

公开(公告)日：2005-06-28

申请号：US09604067

申请日：2000-06-26

Applicant: Ming-Dou Ker ,  Mau-Lin Wu

Inventor： Ming-Dou Ker ,  Mau-Lin Wu

IPC: H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0266

Abstract: A new ESD (Electrostatic Discharge) protection circuit with well-triggered PMOS is provided for application in power-rail ESD protection. A PMOS device is connected between the VDD and VSS power lines to sustain the ESD overstress current during the time that the ESD voltage is applied between the VDD and the VSS power lines. In deep submicron CMOS p-substrate technology, the weak point of ESD overstress control is typically associated with the NMOS device. For this reason, the invention uses a power-rail ESD clamp circuit that incorporates a PMOS device. Applying gate-coupled and N-well triggering techniques, the PMOS can be turned on more efficiently when the ESD overstress is present between the power lines. For p-substrate CMOS technology, it is difficult to couple a high voltage to the substrate of the NMOS device while high voltage is readily coupled to the N-well of a PMOS device. The proposed ESD clamp circuit can be applied efficiently to protect the ESD overstress between power rails.

Abstract translation: 提供了具有良好触发PMOS的新型ESD（静电放电）保护电路，用于电力轨道ESD保护。 在VDD和VSS电源线之间施加ESD电压的时间期间，PMOS器件连接在VDD和VSS电源线之间以维持ESD过应力电流。 在深亚微米CMOS p衬底技术中，ESD过应力控制的弱点通常与NMOS器件相关。 因此，本发明使用包含PMOS器件的电力 - 轨道ESD钳位电路。 应用栅极耦合和N阱触发技术，当电源线之间存在ESD过应力时，可以更有效地开启PMOS。 对于p衬底CMOS技术，难以将高电压耦合到NMOS器件的衬底，同时高电压容易地耦合到PMOS器件的N阱。 提出的ESD钳位电路可以有效地应用于保护电源轨之间的ESD过载。

公开(公告)号：US20090285315A1

公开(公告)日：2009-11-19

申请号：US12121334

申请日：2008-05-15

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: H04L27/28

CPC classification number: H04L25/022 ,  H04L27/2647

Abstract: An apparatus and a method for adaptive channel estimation and a coherent bandwidth estimation apparatus are provided. The adaptive channel estimation apparatus includes a first channel estimator, a coherent bandwidth estimator and a second channel estimator. The first channel estimator uses a predetermined approach to calculate a first channel response of each tone of an orthogonal frequency-division multiplexing (OFDM) signal. The coherent bandwidth estimator is coupled to the first channel estimator for calculating a coherent bandwidth according to the first channel responses. The second channel estimator is coupled to the first channel estimator and the coherent bandwidth estimator. For each of the tones, the second channel estimator calculates a weighted average according to the coherent bandwidth and the first channel responses of several adjacent tones including the aforementioned tone. The second channel estimator outputs the weighted average as the second channel response of the aforementioned tone.

Abstract translation: 提供了一种用于自适应信道估计的装置和方法以及相干带宽估计装置。 自适应信道估计装置包括第一信道估计器，相干带宽估计器和第二信道估计器。 第一信道估计器使用预定的方法来计算正交频分复用（OFDM）信号的每个音调的第一信道响应。 相干带宽估计器耦合到第一信道估计器，用于根据第一信道响应来计算相干带宽。 第二信道估计器耦合到第一信道估计器和相干带宽估计器。 对于每个音调，第二信道估计器根据相干带宽和包括前述音调的几个相邻音调的第一信道响应来计算加权平均。 第二信道估计器输出加权平均值作为上述音调的第二信道响应。

公开(公告)号：US07424664B2

公开(公告)日：2008-09-09

申请号：US11163398

申请日：2005-10-17

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: H03M13/00

CPC classification number: H04L1/0045 ,  H03M13/09 ,  H04L1/0052 ,  H04L1/0061 ,  H04L1/0072 ,  H04L1/1829

Abstract: A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.

Abstract translation: 用于接收机的重复检测电路包括用于产生帧头信息的CRC值的CRC发生器和耦合到CRC发生器的控制电路。 控制电路具有第一输出，第二输出和控制输入。 当控制输入未设定时，控制电路在第一个输出端输出CRC值。 当控制输入被设置时，控制电路在第二个输出端输出CRC值。 缓冲器具有耦合到控制电路的第一输出的输入。 比较电路具有耦合到缓冲器的输出和耦合到控制电路的第二输出的另一个输入的输入。 比较电路将控制电路的第二输出端的CRC值与存储在缓冲器中的CRC值进行比较，并在检测到匹配时输出重复指示。