Abstract:
An OFDM DCM demodulation method is provided. The OFDM DCM demodulation method mainly includes the following steps. First, calculate a log likelihood of a first demodulation mode. Then calculate a log likelihood of a second demodulation mode. Finally, calculate a demodulation output according to the log likelihoods of the first demodulation mode and the second demodulation mode. The demodulation output may serve as an output of a demodulator of a receiving end of a DCM communication system.
Abstract:
An apparatus and a method for adaptive channel estimation and a coherent bandwidth estimation apparatus are provided. The adaptive channel estimation apparatus includes a first channel estimator, a coherent bandwidth estimator and a second channel estimator. The first channel estimator uses a predetermined approach to calculate a first channel response of each tone of an orthogonal frequency-division multiplexing (OFDM) signal. The coherent bandwidth estimator is coupled to the first channel estimator for calculating a coherent bandwidth according to the first channel responses. The second channel estimator is coupled to the first channel estimator and the coherent bandwidth estimator. For each of the tones, the second channel estimator calculates a weighted average according to the coherent bandwidth and the first channel responses of several adjacent tones including the aforementioned tone. The second channel estimator outputs the weighted average as the second channel response of the aforementioned tone.
Abstract:
A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.
Abstract:
Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.
Abstract:
Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.
Abstract:
A layout form ESD-protection MOS transistors include gate electrodes of the ESD-protection MOS transistors being formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. The ESD protection transistors are NMOS and PMOS. The source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes. The wider ends of the gate electrodes straddle the peripheral boundaries of the active region. A modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner transistors.
Abstract:
A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying “PAD” to replace “PCD” into “pre-selection” subgroups with “max-and-zero” property, the invention can reduce the implementation cost without performance degradation.
Abstract:
An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.
Abstract:
In a wireless communication method and system, a data/pilot constellation is modulated and generated based on input information bits. Channel estimation (CE) sequence in frequency-domain is off-line generated. The frequency-domain channel estimation sequence is transformed into a time-domain channel estimation sequence by ideal IFFT to avoid IFFT (Inverse Fast Fourier Transform) impact to EVM (Error Vector Magnitude) performance. Off-line resealing the time-domain CE sequence, multiplied by a rescaling coefficient, in time-domain improves EVM performance. Further, the time-domain channel estimation sequence is off-line quantized.
Abstract:
A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying “PAD” to replace “PCD” into “pre-selection” subgroups with “max-and-zero” property, the invention can reduce the implementation cost without performance degradation.