Device layout to improve ESD robustness in deep submicron CMOS technology
    1.
    发明授权
    Device layout to improve ESD robustness in deep submicron CMOS technology 有权
    器件布局,以提高深亚微米CMOS技术的ESD鲁棒性

    公开(公告)号:US06750517B1

    公开(公告)日:2004-06-15

    申请号:US09706206

    申请日:2000-11-06

    Abstract: A layout form ESD-protection MOS transistors include gate electrodes of the ESD-protection MOS transistors being formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. The ESD protection transistors are NMOS and PMOS. The source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes. The wider ends of the gate electrodes straddle the peripheral boundaries of the active region. A modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner transistors.

    Abstract translation: ESD保护MOS晶体管的布局形式包括在有源区的外围形成有较宽端的ESD保护MOS晶体管的栅电极,由此晶体管具有改善的导通均匀性。 ESD保护晶体管是NMOS和PMOS。 用于晶体管的源极接触和漏极接触位于有源区的周边的内侧,留下用于栅电极较宽端的空间。 栅电极的较宽端跨越有源区的周边边界。 在高耐压I / O电路中为层叠的NMOS和PMOS器件提供了改进的布局样式,其较宽端仅提供在内部晶体管上。

    Power-rail ESD clamp circuits with well-triggered PMOS
    2.
    发明授权
    Power-rail ESD clamp circuits with well-triggered PMOS 有权
    具有良好触发的PMOS的电源轨ESD钳位电路

    公开(公告)号:US06912109B1

    公开(公告)日:2005-06-28

    申请号:US09604067

    申请日:2000-06-26

    CPC classification number: H01L27/0266

    Abstract: A new ESD (Electrostatic Discharge) protection circuit with well-triggered PMOS is provided for application in power-rail ESD protection. A PMOS device is connected between the VDD and VSS power lines to sustain the ESD overstress current during the time that the ESD voltage is applied between the VDD and the VSS power lines. In deep submicron CMOS p-substrate technology, the weak point of ESD overstress control is typically associated with the NMOS device. For this reason, the invention uses a power-rail ESD clamp circuit that incorporates a PMOS device. Applying gate-coupled and N-well triggering techniques, the PMOS can be turned on more efficiently when the ESD overstress is present between the power lines. For p-substrate CMOS technology, it is difficult to couple a high voltage to the substrate of the NMOS device while high voltage is readily coupled to the N-well of a PMOS device. The proposed ESD clamp circuit can be applied efficiently to protect the ESD overstress between power rails.

    Abstract translation: 提供了具有良好触发PMOS的新型ESD(静电放电)保护电路,用于电力轨道ESD保护。 在VDD和VSS电源线之间施加ESD电压的时间期间,PMOS器件连接在VDD和VSS电源线之间以维持ESD过应力电流。 在深亚微米CMOS p衬底技术中,ESD过应力控制的弱点通常与NMOS器件相关。 因此,本发明使用包含PMOS器件的电力 - 轨道ESD钳位电路。 应用栅极耦合和N阱触发技术,当电源线之间存在ESD过应力时,可以更有效地开启PMOS。 对于p衬底CMOS技术,难以将高电压耦合到NMOS器件的衬底,同时高电压容易地耦合到PMOS器件的N阱。 提出的ESD钳位电路可以有效地应用于保护电源轨之间的ESD过载。

    Current stimulator
    3.
    发明授权
    Current stimulator 有权
    当前刺激器

    公开(公告)号:US08892202B2

    公开(公告)日:2014-11-18

    申请号:US13439365

    申请日:2012-04-04

    CPC classification number: A61N1/025 A61N1/36125 H01L2924/0002 H01L2924/00

    Abstract: The disclosure relates to a current stimulator, which comprises a high voltage output module, a voltage control module and a charge pump module. The high voltage output module includes a plurality of stacked transistors, and receives an input control signal able to turn on/off the current stimulator and a first voltage. A second voltage is generated by adding the voltages output by all the transistors to the first voltage and then output to the voltage control module. The voltage control module outputs a voltage control signal able to stabilize the stimulus current for the load according to the second voltage and the load impedance variation. The charge pump regulates the first voltage according to the voltage control signal, and outputs the regulated first voltage to the high voltage output module. Thereby, the current stimulator can adaptively stabilize the stimulus current, responding to load impedance variation.

    Abstract translation: 本公开涉及一种电流刺激器,其包括高压输出模块,电压控制模块和电荷泵模块。 高电压输出模块包括多个堆叠的晶体管,并且接收能够接通/关断电流刺激器的输入控制信号和第一电压。 通过将由所有晶体管输出的电压加到第一电压然后输出到电压控制模块来产生第二电压。 电压控制模块根据第二电压和负载阻抗变化输出能够稳定负载的刺激电流的电压控制信号。 电荷泵根据电压控制信号调节第一电压,并将调节的第一电压输出到高电压输出模块。 因此,电流刺激器可以自适应地稳定刺激电流,响应于负载阻抗变化。

    Load-adaptive bioelectric current stimulator
    4.
    发明授权
    Load-adaptive bioelectric current stimulator 有权
    负载自适应生物电流刺激器

    公开(公告)号:US08527061B2

    公开(公告)日:2013-09-03

    申请号:US13224166

    申请日:2011-09-01

    CPC classification number: A61N1/36521

    Abstract: The disclosure relates to a load-adaptive bioelectrical current stimulator, which comprises a current output module, an adaptation module and a control module. The current output module generates a stimulus current to an electrode. The adaptation module detects the electrical status of the stimulus current passing through the electrode and generates a feedback signal to the control module. According to the feedback signal, the control module controls the current output module to stabilize the output status of the stimulus current adaptively. Thereby, the load-adaptive bioelectrical current stimulator can use the feedback control mechanism to regulate the value of the stimulus current to adapt to variation of load impedance.

    Abstract translation: 本公开涉及一种负载自适应生物电流电流刺激器,其包括电流输出模块,适配模块和控制模块。 电流输出模块产生到电极的刺激电流。 适配模块检测通过电极的刺激电流的电气状态,并产生一个到控制模块的反馈信号。 根据反馈信号,控制模块控制电流输出模块,自适应地稳定激励电流的输出状态。 因此,负载自适应生物电流电流刺激器可以使用反馈控制机制来调节刺激电流的值以适应负载阻抗的变化。

    CURRENT STIMULATOR
    5.
    发明申请
    CURRENT STIMULATOR 有权
    电流刺激仪

    公开(公告)号:US20130172958A1

    公开(公告)日:2013-07-04

    申请号:US13439365

    申请日:2012-04-04

    CPC classification number: A61N1/025 A61N1/36125 H01L2924/0002 H01L2924/00

    Abstract: The disclosure relates to a current stimulator, which comprises a high voltage output module, a voltage control module and a charge pump module. The high voltage output module includes a plurality of stacked transistors, and receives an input control signal able to turn on/off the current stimulator and a first voltage. A second voltage is generated by adding the voltages output by all the transistors to the first voltage and then output to the voltage control module. The voltage control module outputs a voltage control signal able to stabilize the stimulus current for the load according to the second voltage and the load impedance variation. The charge pump regulates the first voltage according to the voltage control signal, and outputs the regulated first voltage to the high voltage output module. Thereby, the current stimulator can adaptively stabilize the stimulus current, responding to load impedance variation.

    Abstract translation: 本公开涉及一种电流刺激器,其包括高压输出模块,电压控制模块和电荷泵模块。 高电压输出模块包括多个堆叠的晶体管,并且接收能够接通/关断电流刺激器的输入控制信号和第一电压。 通过将由所有晶体管输出的电压加到第一电压然后输出到电压控制模块来产生第二电压。 电压控制模块根据第二电压和负载阻抗变化输出能够稳定负载的刺激电流的电压控制信号。 电荷泵根据电压控制信号调节第一电压,并将调节的第一电压输出到高电压输出模块。 因此,电流刺激器可以自适应地稳定刺激电流,响应于负载阻抗变化。

    Polydiode structure for photo diode
    6.
    发明授权
    Polydiode structure for photo diode 有权
    光电二极管的多晶硅结构

    公开(公告)号:US08367457B2

    公开(公告)日:2013-02-05

    申请号:US13205017

    申请日:2011-08-08

    CPC classification number: H01L31/103 H01L27/14609 H01L31/105

    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

    Abstract translation: 用于将入射光信号转换成电信号的集成电路装置包括半导体衬底,形成在半导体衬底内部的阱区,形成在阱区上的电介质层和用于接收入射光信号的多晶硅层,形成 包括p型部分,n型部分和设置在p型和n型部分之间的未掺杂部分,其中阱区被偏置以控制多晶硅层以提供电信号 。

    ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    7.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权
    静电放电保护装置

    公开(公告)号:US20120146151A1

    公开(公告)日:2012-06-14

    申请号:US13040415

    申请日:2011-03-04

    CPC classification number: H01L23/62 H01L27/0262 H01L2924/0002 H01L2924/00

    Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

    Abstract translation: 公开了一种包括衬底,第一掺杂区域,第二掺杂区域和第三掺杂区域的静电放电(ESD)保护器件,栅极和多个触点。 基板包括第一导电类型。 第一掺杂区域形成在衬底中并且包括第二导电类型。 第二掺杂区域形成在衬底中并且包括第二导电类型。 第三掺杂区域形成在衬底中,包括第一导电类型并且位于第一和第二掺杂区域之间。 栅极形成在衬底上,位于第一和第二掺杂区之间,并且包括第一通孔。 触点通过第一通孔以与第三掺杂区域接触。

    ESD PROTECTION CIRCUIT WITH MERGED TRIGGERING MECHANISM
    8.
    发明申请
    ESD PROTECTION CIRCUIT WITH MERGED TRIGGERING MECHANISM 有权
    具有合并触发机制的ESD保护电路

    公开(公告)号:US20110043953A1

    公开(公告)日:2011-02-24

    申请号:US12543468

    申请日:2009-08-18

    CPC classification number: H02H9/046

    Abstract: An ESD protection circuit has a merged triggering mechanism. The ESD protection circuit comprises: an ESD detection circuit, for detecting an ESD voltage to generate a control signal; a first type ESD protection device, for outputting a first trigger current; a second type ESD protection device, for receiving a second trigger current; and a trigger circuit, for constituting a conductive path according to the control signal, such that the trigger circuit can receive the first trigger current from the first type ESD protection device and outputs the second trigger current to the second type ESD protection device.

    Abstract translation: ESD保护电路具有合并的触发机制。 ESD保护电路包括:ESD检测电路,用于检测ESD电压以产生控制信号; 第一类ESD保护装置,用于输出第一触发电流; 第二类ESD保护装置,用于接收第二触发电流; 以及触发电路,用于根据控制信号构成导电路径,使得触发电路可以从第一类ESD保护装置接收第一触发电流,并将第二触发电流输出到第二类ESD保护装置。

    ESD detection circuit and related method thereof
    9.
    发明授权
    ESD detection circuit and related method thereof 有权
    ESD检测电路及其相关方法

    公开(公告)号:US07884617B2

    公开(公告)日:2011-02-08

    申请号:US12334496

    申请日:2008-12-14

    CPC classification number: H02H9/046

    Abstract: An electro-static discharge (ESD) detection circuit is provided. The ESD detection circuit includes: a first power pad for receiving a first supply voltage; a second power pad for receiving a second supply voltage; an RC circuit having an impedance component coupled between the first power pad and a first terminal and having an capacitive component coupled between the first terminal and a second terminal, wherein the second terminal is not directly connected to the second supply voltage; a trigger circuit couples to the first power pad, the second power pad, and the RC circuit, for generating an ESD trigger signal according to a voltage level at the first terminal and a voltage level at the second terminal, and a bias circuit coupled between the first power pad and the second power pad for providing a bias voltage to the second terminal.

    Abstract translation: 提供静电放电(ESD)检测电路。 ESD检测电路包括:用于接收第一电源电压的第一电源焊盘; 用于接收第二电源电压的第二电源焊盘; RC电路,其阻抗分量耦合在第一功率焊盘和第一端子之间,并具有耦合在第一端子和第二端子之间的电容部件,其中第二端子不直接连接到第二电源电压; 触发电路耦合到第一功率焊盘,第二功率焊盘和RC电路,用于根据第一端子处的电压电平和第二端子处的电压电平产生ESD触发信号,以及耦合在第二端子之间的偏置电路 所述第一功率垫和所述第二功率垫用于向所述第二端子提供偏置电压。

    Electrostatic discharge protection device and related circuit
    10.
    发明授权
    Electrostatic discharge protection device and related circuit 有权
    静电放电保护装置及相关电路

    公开(公告)号:US07880195B2

    公开(公告)日:2011-02-01

    申请号:US12329636

    申请日:2008-12-08

    CPC classification number: H01L27/0262

    Abstract: An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.

    Abstract translation: ESD保护装置包括P型衬底,设置在P型衬底中的第一衬底触发的可控硅整流器(STSCR)和设置在P型衬底中的第二STSCR。 第一STSCR包括第一N阱,第一P阱,第一N +扩散区,第一P +扩散区和第一触发节点。 第二STSCR包括电连接到第一N阱的第二N阱,电连接到第一P阱的第二P阱,电连接到第一P +扩散区的第二N +扩散区,第二P +扩散 电连接到第一N +扩散区域的区域和第二触发器节点。 可以减小集成电路的布局区域和引脚到针脚ESD电流路径。

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