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公开(公告)号：US20190058554A1
公开(公告)日：2019-02-21
申请号：US16105109
申请日：2018-08-20
Applicant: MEDIATEK INC.
Inventor： Pei-Kai Liao , Ming-Che Lu , Yen-Shuo Chang , Chien-Hwa Hwang
Abstract: An efficient Hybrid Automatic Repeat Request (HARQ) operation for low-latency and high-performance services in one radio access technology (RAT) in a wireless communication network is proposed. Under the proposed single HARQ operation scheme, an adaptive HARQ-ACK feedback timing is applied based on UE conditions and UE capability to support the tradeoff between low-latency and high-performance applications. In one embodiment, UE signals the network its HARQ-ACK timing capability. Furthermore, an adaptive number of HARQ processes is applied with a fixed HARQ soft buffer size because the hardware cost for HARQ soft buffer does not linearly increase with the number of HARQ processes. In one embodiment, UE determines a nominal HARQ soft buffer size and HARQ soft buffer size for each HARQ process based on a network-configured HARQ process number.
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Patent Agency Ranking
公开(公告)号：US20180212628A1
公开(公告)日：2018-07-26
申请号：US15878357
申请日：2018-01-23
Applicant: MediaTek Inc.
Inventor： Ju-Ya Chen , Cheng-Yi Hsu , Yen-Shuo Chang , Wei-Jen Chen , Mao-Ching Chiu , Timothy Perrin Fisher-Jeffes , Chong-You Lee
CPC classification number: H03M13/2792 , H03M13/1105 , H03M13/116 , H03M13/255 , H03M13/2707 , H04L1/0041 , H04L1/0058 , H04L1/0071
Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.
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公开(公告)号：US11005602B2
公开(公告)日：2021-05-11
申请号：US16149085
申请日：2018-10-01
Applicant: MediaTek Inc.
Inventor： Wei-De Wu , Timothy Perrin Fisher-Jeffes , Yen-Shuo Chang , Chia-Wei Tai , Hsien-Kai Hsin , Pei-Kai Liao
Abstract: Techniques and examples of hybrid automatic repeat request (HARQ) buffer size design for communication systems are described. A user equipment (UE) communicates with a serving cell of a wireless network using a HARQ mechanism, with the communicating involving: (a) determining, by the processor, a respective size of each buffer of a plurality of buffers corresponding to a plurality of HARQ processes on a per-HARQ process basis; and (b) storing, by the processor, respective information in each buffer of the plurality of buffers for a corresponding HARQ process among the plurality of HARQ processes.
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公开(公告)号：US10958290B2
公开(公告)日：2021-03-23
申请号：US16543783
申请日：2019-08-19
Applicant: MediaTek Inc.
Inventor： Wei-Jen Chen , Ju-Ya Chen , Yen-Shuo Chang , Timothy Perrin Fisher-Jeffes , Mao-Ching Chiu , Cheng-Yi Hsu , Chong-You Lee
Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
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公开(公告)号：US20180212626A1
公开(公告)日：2018-07-26
申请号：US15878350
申请日：2018-01-23
Applicant: MediaTek Inc.
Inventor： Wei-Jen Chen , Ju-Ya Chen , Yen-Shuo Chang , Timothy Perrin Fisher-Jeffes , Mao-Ching Chiu , Cheng-Yi Hsu , Chong-You Lee
Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
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公开(公告)号：US20170250712A1
公开(公告)日：2017-08-31
申请号：US15594239
申请日：2017-05-12
Applicant: MediaTek Inc.
Inventor： Mao-Ching Chiu , Chong-You Lee , Cheng-Yi Hsu , Timothy Perrin Fisher-Jeffes , Yen-Shuo Chang , Wei-Jen Chen , Ju-Ya Chen
CPC classification number: H03M13/1168 , H03M13/033 , H03M13/116 , H03M13/616 , H03M13/6306 , H03M13/6516 , H04L1/0057 , H04L1/0068 , H04L1/1819
Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value
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