METHOD AND APPARATUS FOR INTERFERENCE CANCELLATION BY A USER EQUIPMENT
    5.
    发明申请
    METHOD AND APPARATUS FOR INTERFERENCE CANCELLATION BY A USER EQUIPMENT 有权
    用户设备干扰消除的方法和装置

    公开(公告)号:US20170077968A1

    公开(公告)日:2017-03-16

    申请号:US14854067

    申请日:2015-09-15

    Applicant: MEDIATEK Inc.

    CPC classification number: H04B1/0475 H04B7/0452 H04L25/03891 H04L27/0012

    Abstract: An apparatus for interference cancellation includes: a front end processing circuit, for receiving at least an interference signal and a desire signal; an inner processing circuit, for channel/noise estimation and for suppressing the interference signal; and a MIMO (multi-input multi-output) processing circuit, for blindly detecting an interference parameter of the interference signal based on the suppressed interference signal, and for jointly cancelling the interference signal from the desire signal and for demodulating the desire signal based on the detected interference parameter and the channel/noise estimation from the inner processing circuit.

    Abstract translation: 用于干扰消除的装置包括:用于至少接收干扰信号和期望信号的前端处理电路; 内部处理电路,用于信道/噪声估计并用于抑制干扰信号; 以及MIMO(多输入多输出)处理电路,用于基于所抑制的干扰信号盲目地检测干扰信号的干扰参数,并且从所述期望信号共同抵消干扰信号,并基于 检测到的干扰参数和来自内部处理电路的信道/噪声估计。

    Method and apparatus for error correction coding in communication

    公开(公告)号:US10608665B2

    公开(公告)日:2020-03-31

    申请号:US15917260

    申请日:2018-03-09

    Applicant: MEDIATEK INC.

    Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.

    Location of interleaver with LDPC code

    公开(公告)号:US10432227B2

    公开(公告)日:2019-10-01

    申请号:US15878350

    申请日:2018-01-23

    Applicant: MediaTek Inc.

    Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

    METHOD AND APPARATUS FOR COMMUNICATION
    9.
    发明申请

    公开(公告)号:US20180227077A1

    公开(公告)日:2018-08-09

    申请号:US15888733

    申请日:2018-02-05

    Applicant: MEDIATEK INC.

    Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

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