ERROR CORRECTING CODE ENCODING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

    公开(公告)号:US20240340025A1

    公开(公告)日:2024-10-10

    申请号:US18520707

    申请日:2023-11-28

    IPC分类号: H03M13/11 H03M13/00

    CPC分类号: H03M13/1168 H03M13/616

    摘要: A semiconductor device may include an error correcting code (ECC) encoder that encodes a codeword based on a parity check matrix and generates the encoded codeword including an information bit and a parity bit. The parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit. The parity part includes a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure, a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a block matrix D composed of a first sub-matrix, and a block matrix E including a first sub-matrix and a masked (1−(a+1))-th sub-matrix. A location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E.

    Non-binary low density parity check (NB-LDPC) codes for communication systems
    9.
    发明申请
    Non-binary low density parity check (NB-LDPC) codes for communication systems 有权
    用于通信系统的非二进制低密度奇偶校验(NB-LDPC)码

    公开(公告)号:US20160094246A1

    公开(公告)日:2016-03-31

    申请号:US14850539

    申请日:2015-09-10

    IPC分类号: H03M13/11

    摘要: A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. The device receives a non-binary low density parity check (NB-LDPC) coded signal. The device then decodes the NB-LDPC coded signal using a NB-LDPC matrix to generate estimates of information bits encoded therein. The NB-LDPC matrix is characterized by a base proto-matrix having elements that represent sub-matrices, and the elements are selected from a finite Galois field that includes symbols. In another example, the device encodes other information bits using a generator matrix to generate another NB-LDPC coded signal and then transmits this other NB-LDPC coded signal.

    摘要翻译: 通信设备(可选地,设备)包括被配置为支持与其他通信设备的通信并且生成和处理用于这种通信的信号的处理器。 在一些示例中,设备包括通信接口和处理器以及其他可能的电路,组件,元件等,以支持与其他通信设备的通信,并且生成和处理用于这种通信的信号。 该装置接收非二进制低密度奇偶校验(NB-LDPC)编码信号。 然后,装置使用NB-LDPC矩阵对NB-LDPC编码信号进行解码,以产生其中编码的信息比特的估计。 NB-LDPC矩阵的特征在于具有表示子矩阵的元素的基本原理矩阵,并且元素从包括符号的有限伽罗瓦域中选择。 在另一示例中,设备使用生成器矩阵对其他信息比特进行编码,以生成另一个NB-LDPC编码信号,然后发送另一个NB-LDPC编码信号。

    PARALLEL BIT INTERLEAVER
    10.
    发明申请
    PARALLEL BIT INTERLEAVER 审中-公开
    并行位交互

    公开(公告)号:US20150333771A1

    公开(公告)日:2015-11-19

    申请号:US14804466

    申请日:2015-07-21

    发明人: Mihail PETROV

    IPC分类号: H03M13/27 H03M13/11

    摘要: A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

    摘要翻译: 一种将位置换处理应用于由Q位的N个循环块组成的QC LDPC码字的比特交织方法,每个将经处理的码字分成每个M位的星座字,并将循环块置换处理应用于循环 块,其中码字被分成M / F个循环块的F×N / M个折叠部分,并且星座词各自与折叠部分之一相关联,并且应用比特置换处理,使得星座词各自 在排列处理之后由相关部分中的M / F个不同循环块中的每一个的F位组成。