公开(公告)号：US08468417B2

公开(公告)日：2013-06-18

申请号：US12388305

申请日：2009-02-18

申请人： Mehdi Asnaashari ,  Ronald Yamada ,  Siamack Nemazie ,  Jui-Yao (“Ray”) Yang

发明人： Mehdi Asnaashari ,  Ronald Yamada ,  Siamack Nemazie ,  Jui-Yao (“Ray”) Yang

IPC分类号： H03M13/00

CPC分类号： G06F11/1048 ,  G06F11/10 ,  G06F11/1004 ,  G06F13/28 ,  G06F21/64 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/13 ,  H03M13/29

摘要： The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

公开(公告)号：US08239614B2

公开(公告)日：2012-08-07

申请号：US12397402

申请日：2009-03-04

申请人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie ,  Dale P. McNamara

发明人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie ,  Dale P. McNamara

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7208

摘要： The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

摘要翻译： 本公开包括用于存储块选择的方法和装置。 在一个或多个实施例中，存储器控制器包括耦合到具有与其相关联的多组平面的一个或多个存储器件的控制电路，每个组包括组织成超级块的至少两个物理块平面，每个超级块包括物理块 从至少两个平面的每一个。 控制电路被配置为接收与写入操作相关联的第一未分配逻辑块地址（LBA），并且确定多个组中所选择的一个组内的特定空闲超级块以接收与写入操作相关联的数据。

公开(公告)号：US20100228928A1

公开(公告)日：2010-09-09

申请号：US12397402

申请日：2009-03-04

申请人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie ,  Dale P. McNamara

发明人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie ,  Dale P. McNamara

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7208

摘要： The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

摘要翻译： 本公开包括用于存储块选择的方法和装置。 在一个或多个实施例中，存储器控制器包括耦合到具有与其相关联的多组平面的一个或多个存储器件的控制电路，每个组包括组织成超级块的至少两个物理块平面，每个超级块包括物理块 从至少两个平面的每一个。 控制电路被配置为接收与写入操作相关联的第一未分配逻辑块地址（LBA），并且确定多个组中所选择的一个组内的特定空闲超级块以接收与写入操作相关联的数据。

公开(公告)号：US20100228940A1

公开(公告)日：2010-09-09

申请号：US12397396

申请日：2009-03-04

申请人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie

发明人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F11/00

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C29/76

摘要： Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.

摘要翻译： 各种实施例包括具有组织成超块的物理块的至少两个平面的一个或多个存储器件，每个超级块包括来自至少两个平面中的每一个的物理块。 实施例包括确定平面内的有缺陷的块。 如果没有将特定块位置处的块都确定为有缺陷，则实施例包括将特定块位置处的块分配给超块，并且如果确定特定块位置处的一个或多个块被确定为有缺陷， 实施例包括：将确定为有缺陷的特定块位置的块分配给超块; 以及针对被确定为有缺陷的特定块位置处的所述一个或多个块中的每个块为所述超级块分配相应的替换块。 相应的替换块从包括被确定为有缺陷的相应块的平面中的相应一个中的多个块中选择。

公开(公告)号：US20100211834A1

公开(公告)日：2010-08-19

申请号：US12388305

申请日：2009-02-18

申请人： Mehdi Asnaashari ,  Ronald Yamada ,  Siamack Nemazie ,  Jui-Yao ("Ray") Yang

发明人： Mehdi Asnaashari ,  Ronald Yamada ,  Siamack Nemazie ,  Jui-Yao ("Ray") Yang

IPC分类号： G11C29/04 ,  H03M13/05 ,  G06F11/07 ,  G06F11/22

CPC分类号： G06F11/1048 ,  G06F11/10 ,  G06F11/1004 ,  G06F13/28 ,  G06F21/64 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/13 ,  H03M13/29

摘要： The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

摘要翻译： 本公开包括用于存储器控制器中的数据完整性的方法，设备和系统。 一个存储器控制器实施例包括耦合到主机接口的主机接口和第一错误检测电路。 存储器控制器可以包括耦合到存储器接口的存储器接口和第二错误检测电路。 第一错误检测电路可以被配置为计算从主机接口接收的数据的错误检测数据，并且检查发送到主机接口的数据的完整性。 第二错误检测电路可以被配置为计算发送到存储器接口的数据和第一纠错数据的纠错数据，并且检查数据的完整性和从存储器接口接收到的第一纠错数据。

公开(公告)号：US08751731B2

公开(公告)日：2014-06-10

申请号：US13567680

申请日：2012-08-06

申请人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie ,  Dale P. McNamara

发明人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie ,  Dale P. McNamara

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7208

摘要： The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

摘要翻译： 本公开包括用于存储块选择的方法和装置。 在一个或多个实施例中，存储器控制器包括耦合到具有与其相关联的多组平面的一个或多个存储器件的控制电路，每个组包括组织成超级块的至少两个物理块平面，每个超级块包括物理块 从至少两个平面的每一个。 控制电路被配置为接收与写入操作相关联的第一未分配逻辑块地址（LBA），并且确定多个组中所选择的一个组内的特定空闲超级块以接收与写入操作相关联的数据。

公开(公告)号：US20120303931A1

公开(公告)日：2012-11-29

申请号：US13567680

申请日：2012-08-06

申请人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie ,  Dale P. McNamara

发明人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie ,  Dale P. McNamara

IPC分类号： G06F12/06

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7208

摘要： The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

摘要翻译： 本公开包括用于存储块选择的方法和装置。 在一个或多个实施例中，存储器控制器包括耦合到具有与其相关联的多组平面的一个或多个存储器件的控制电路，每个组包括组织成超级块的至少两个物理块平面，每个超级块包括物理块 从至少两个平面的每一个。 控制电路被配置为接收与写入操作相关联的第一未分配逻辑块地址（LBA），并且确定多个组中所选择的一个组内的特定空闲超级块以接收与写入操作相关联的数据。

公开(公告)号：US08312245B2

公开(公告)日：2012-11-13

申请号：US13347054

申请日：2012-01-10

申请人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie

发明人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C29/76

摘要： One or more embodiments comprise control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks. The control circuitry can be configured to: determine defective physical blocks among the number of planes; responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and responsive to one or more of the physical blocks at a particular block position being determined to be defective, assign non-defective physical blocks at the particular block position to a super block and assign a replacement physical block to the super block for the respective defective physical blocks at the particular block position, the replacement physical block selected from a number of physical blocks within a respective plane that includes a respective defective physical block.

摘要翻译： 一个或多个实施例包括耦合到具有组织成超级块的物理块的多个平面的一个或多个存储器设备的控制电路。 控制电路可以被配置为：确定多个平面之间的有缺陷的物理块; 响应于被确定为有缺陷的特定块位置处的任何物理块都不被分配给特定块位置的物理块到超级块; 并且响应于被确定为有缺陷的特定块位置处的一个或多个物理块，将特定块位置处的无缺陷物理块分配给超级块，并将相应缺陷的替换物理块分配给超级块 在特定块位置处的物理块，从包括相应的有缺陷的物理块的相应平面内的多个物理块中选择的替换物理块。

公开(公告)号：US20120124304A1

公开(公告)日：2012-05-17

申请号：US13347054

申请日：2012-01-10

申请人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie

发明人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie

IPC分类号： G06F12/12

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C29/76

摘要： One or more embodiments comprise control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks. The control circuitry can be configured to: determine defective physical blocks among the number of planes; responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and responsive to one or more of the physical blocks at a particular block position being determined to be defective, assign non-defective physical blocks at the particular block position to a super block and assign a replacement physical block to the super block for the respective defective physical blocks at the particular block position, the replacement physical block selected from a number of physical blocks within a respective plane that includes a respective defective physical block.

摘要翻译： 一个或多个实施例包括耦合到具有组织成超级块的物理块的多个平面的一个或多个存储器设备的控制电路。 控制电路可以被配置为：确定多个平面之间的有缺陷的物理块; 响应于被确定为有缺陷的特定块位置处的任何物理块都不被分配给特定块位置的物理块到超级块; 并且响应于被确定为有缺陷的特定块位置处的一个或多个物理块，将特定块位置处的无缺陷物理块分配给超级块，并将相应缺陷的替换物理块分配给超级块 在特定块位置处的物理块，从包括相应的有缺陷的物理块的相应平面内的多个物理块中选择的替换物理块。

公开(公告)号：US08095765B2

公开(公告)日：2012-01-10

申请号：US12397396

申请日：2009-03-04

申请人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie

发明人： Mehdi Asnaashari ,  Alan Chen ,  Siamack Nemazie

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C29/76

摘要： Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.

摘要翻译： 各种实施例包括具有组织成超块的物理块的至少两个平面的一个或多个存储器件，每个超级块包括来自至少两个平面中的每一个的物理块。 实施例包括确定平面内的有缺陷的块。 如果没有将特定块位置处的块都确定为有缺陷，则实施例包括将特定块位置处的块分配给超块，并且如果确定特定块位置处的一个或多个块被确定为有缺陷， 实施例包括：将确定为有缺陷的特定块位置的块分配给超块; 以及针对被确定为有缺陷的特定块位置处的所述一个或多个块中的每个块为所述超级块分配相应的替换块。 相应的替换块从包括被确定为有缺陷的相应块的平面中的相应一个中的多个块中选择。