公开(公告)号：US20240322845A1

公开(公告)日：2024-09-26

申请号：US18680900

申请日：2024-05-31

申请人： KIOXIA CORPORATION

发明人： Riki SUZUKI ,  Toshikatsu HIDA ,  Osamu TORII ,  Hiroshi YAO ,  Kiyotaka IWASAKI

IPC分类号： H03M13/35 ,  G06F3/06 ,  G06F11/10 ,  G11B20/18 ,  G11C7/10 ,  G11C29/04 ,  G11C29/52 ,  H03M13/29

CPC分类号： H03M13/35 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C29/52 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2957 ,  G11B20/1833 ,  G11C7/1006 ,  G11C2029/0411

摘要： According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

公开(公告)号：US11936400B2

公开(公告)日：2024-03-19

申请号：US17749636

申请日：2022-05-20

申请人： Samsung Electronics Co., Ltd. ,  Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

发明人： Kwonjong Lee ,  Seunghyun Lee ,  Sanghyo Kim ,  Minyoung Chung ,  Hyosang Ju ,  Jisang Park

IPC分类号： H03M13/29 ,  H03M13/25 ,  H03M13/09 ,  H03M13/11 ,  H03M13/13 ,  H04L1/00

CPC分类号： H03M13/29 ,  H03M13/253 ,  H03M13/098 ,  H03M13/1157 ,  H03M13/13 ,  H04L1/0063

摘要： The disclosure relates to a fifth generation (5G) or sixth generation (6G) communication system for supporting a higher data transmission rate. An encoding apparatus may obtain state-indicator information indicating a state of each of bits included in the polar code based on an index set of the bits, identify a weak-bit or a second weak-bit corresponding to a parity bit candidate position preset according to an interconnection within a parity-check (PC)-chain of the polar code and between PC-chains of the polar code as a parity bit, based on a number of weak-bits determined according to the state-indicator information and a number of bits to be used as parity bits, and obtain a polar code including the identified parity bit.

公开(公告)号：US20230370667A1

公开(公告)日：2023-11-16

申请号：US18139074

申请日：2023-04-25

申请人： Coherent Logix, Incorporated

发明人： Colleen J. McGinn ,  Kevin A. Shelby ,  Peter J. Nysen ,  Michael B. Doerr

IPC分类号： H04N21/266 ,  H04L69/18 ,  H03M13/29 ,  H04N21/61 ,  H04N21/438 ,  H04N21/2381 ,  H03M13/00 ,  H04N21/236 ,  H04L65/70 ,  H04L65/611 ,  H04L65/75

CPC分类号： H04N21/266 ,  H04L69/18 ,  H03M13/29 ,  H03M13/2906 ,  H04N21/6131 ,  H04N21/6112 ,  H04N21/4381 ,  H04N21/2381 ,  H03M13/6583 ,  H03M13/2957 ,  H03M13/2909 ,  H04N21/23605 ,  H04L65/70 ,  H04L65/611 ,  H04L65/764 ,  H03M13/1102

摘要： Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.

公开(公告)号：US11671642B2

公开(公告)日：2023-06-06

申请号：US17550096

申请日：2021-12-14

申请人： Coherent Logix, Incorporated

发明人： Colleen J. McGinn ,  Kevin A. Shelby ,  Peter J. Nysen ,  Michael B. Doerr

IPC分类号： H04N7/16 ,  H04N21/266 ,  H04L69/18 ,  H03M13/29 ,  H04N21/61 ,  H04N21/438 ,  H04N21/2381 ,  H03M13/00 ,  H04N21/236 ,  H04L65/70 ,  H04L65/611 ,  H04L65/75 ,  H03M13/11 ,  H03M13/27

CPC分类号： H04N21/266 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/6583 ,  H04L65/611 ,  H04L65/70 ,  H04L65/764 ,  H04L69/18 ,  H04N21/2381 ,  H04N21/23605 ,  H04N21/4381 ,  H04N21/6112 ,  H04N21/6131 ,  H03M13/1102 ,  H03M13/2732 ,  H03M13/2936

摘要： Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.

公开(公告)号：US11669379B2

公开(公告)日：2023-06-06

申请号：US17728621

申请日：2022-04-25

申请人： Rambus Inc.

发明人： Yuanlong Wang ,  Frederick A. Ware

IPC分类号： G01R31/28 ,  G06F11/07 ,  H03M13/09 ,  H03M13/29 ,  G06F3/06 ,  G06F11/10 ,  H03M13/00 ,  G06F13/42 ,  H04L1/00 ,  H04L1/08 ,  H04L1/1867 ,  G06F11/14

CPC分类号： G06F11/0727 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  G06F11/1044 ,  H04L1/0003 ,  H04L1/0008 ,  H04L2001/0093

摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

公开(公告)号：US11652566B2

公开(公告)日：2023-05-16

申请号：US16603623

申请日：2018-07-30

申请人： Ciena Corporation

发明人： Shahab Oveis Gharan ,  Mohammad Ehsan Seifi ,  Kim B. Roberts

IPC分类号： H04L1/00 ,  H03M13/25 ,  H03M13/29 ,  H03M13/11 ,  H04L1/20 ,  H03M13/03 ,  G06F17/18 ,  G06F17/15

CPC分类号： H04L1/00 ,  G06F17/18 ,  H03M13/03 ,  H03M13/1125 ,  H03M13/253 ,  H03M13/29 ,  H03M13/2948 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0063 ,  H04L1/0064 ,  H04L1/0066 ,  H04L1/203 ,  G06F17/156

摘要： In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.

公开(公告)号：US20190215015A1

公开(公告)日：2019-07-11

申请号：US16357696

申请日：2019-03-19

申请人： TOSHIBA MEMORY CORPORATION

发明人： Shinichi KANNO ,  Hironori UCHIKAWA

IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/35 ,  G11C29/52 ,  G06F13/16 ,  H03M13/00 ,  G06F13/40

CPC分类号： H03M13/2906 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1068 ,  G06F13/1673 ,  G06F13/4068 ,  G11C29/52 ,  H03M13/03 ,  H03M13/29 ,  H03M13/35 ,  H03M13/6561 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

公开(公告)号：US20190171518A1

公开(公告)日：2019-06-06

申请号：US16204022

申请日：2018-11-29

申请人： Burlywood, LLC

发明人： David Christopher Pruett ,  Christopher Bergman ,  Tod Roland Earhart

IPC分类号： G06F11/10 ,  H03M13/29 ,  H03M13/11 ,  H03M13/15 ,  H03M13/09 ,  H03M13/37

CPC分类号： G06F11/1004 ,  G06F11/1012 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/152 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2948 ,  H03M13/3746

摘要： A method of operating a storage controller is provided. The method includes determining encoded data to be written to a storage media by applying at least an initial encoding comprising a first error correcting code type and a subsequent encoding comprising a second error correcting code type. The method further includes writing the encoded data to the storage media, and responsive to reading the encoded data from the storage media, processing the encoded data into primary decoded data using one or more primary decoders employing the second error correcting code type and detecting when data errors arise in the decoded data. The method also includes based at least on detecting one or more data errors in the decoded data, processing the encoded data into secondary decoded data using one or more secondary decoders employing the first error correcting code type.

公开(公告)号：US20190036549A1

公开(公告)日：2019-01-31

申请号：US16132461

申请日：2018-09-16

申请人： Silicon Motion Inc.

发明人： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC分类号： H03M13/29 ,  G06F11/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04 ,  G06F12/0802 ,  G06F12/02 ,  G06F11/14 ,  G11C7/10 ,  H03M13/11 ,  G11C29/52

CPC分类号： H03M13/29 ,  G06F11/10 ,  G06F11/1072 ,  G06F11/1402 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7207 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C29/52 ,  G11C2211/5641 ,  H03M13/1102

摘要： A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

公开(公告)号：US20180198470A1

公开(公告)日：2018-07-12

申请号：US15914638

申请日：2018-03-07

申请人： SK hynix Inc.

发明人： Hyung-Min LEE ,  Jae-Yoon LEE ,  Myeong-Woon JEON

IPC分类号： H03M13/29 ,  G11C16/10

CPC分类号： H03M13/29 ,  G06F11/1012 ,  G06F11/1068 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/293 ,  H03M13/2948 ,  H03M13/2957

摘要： An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ECC) decoding for the first data; when the first ECC decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ECC decoding for the plurality of the remaining data; when the second ECC decoding fails, identifying data, to which the second ECC decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ECC decoding fails, and the second data, to which the second ECC decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.