摘要:
In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.
摘要:
A drive circuit includes a drive unit coupling with data lines for receiving at least one clock signal and a first enable signal to generate a drive signal to drive data lines, and a delay unit electrically coupled with the drive unit for receiving the clock signal and the first enable signal and generating a second enable signal falling subsequent to the first enable signal in a predetermined time interval.
摘要:
A shift register applied on a double-frame-rate LCD is provided. The LCD includes an upper display area with c gate lines, a lower display area with d gate lines, and a gate driving circuit. The gate driving circuit includes a first shift register coupled to the corresponding x gate lines of the upper display area, a second shift register coupled to the corresponding y lines of the lower display area, and a third shift register coupled to the corresponding (c-x) gate lines of the upper display area and the corresponding (d-y) gate lines of the lower display area.
摘要:
A drive circuit includes a drive unit coupling with data lines for receiving at least one clock signal and a first enable signal to generate a drive signal to drive data lines, and a delay unit electrically coupled with the drive unit for receiving the clock signal and the first enable signal and generating a second enable signal falling subsequent to the first enable signal in a predetermined time interval.