摘要:
A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functionality of the cache memory arrays. External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.
摘要:
The power of a signal transmitted from a mobile terminal of a half-duplex TDMA communication system to a base station is controlled by collecting data relating to bit errors in the transmitted signal received on an inbound channel, generating a time-varying statistic of the data. If the time varying statistic indicates that the power should be adjusted, a power control command is embedded in one or more time slots of an outbound channel to the mobile terminal to change the power of the signal. The data may be the bit error rate (BER) reported by a forward error correction decoder and/or returned signal strength information (RSSI). The time varying statistic may be the moving average and standard deviation of the data.