公开(公告)号：US07467204B2

公开(公告)日：2008-12-16

申请号：US11055675

申请日：2005-02-10

申请人： James Stephen Fields, Jr. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields, Jr. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： G06F15/173 ,  G06F15/167

CPC分类号： G06F15/161

摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

公开(公告)号：US09063807B2

公开(公告)日：2015-06-23

申请号：US13594253

申请日：2012-08-24

申请人： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

发明人： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

IPC分类号： G06F7/58 ,  G06F13/14

CPC分类号： G06F7/58 ,  G06F13/14

摘要： A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.

摘要翻译： 随机数生成器包括公平校验器和校正模块，其确保在随机数发生器内将在预定时间段内的完整随机序列输出。

公开(公告)号：US07916722B2

公开(公告)日：2011-03-29

申请号：US12139631

申请日：2008-06-16

申请人： James Stephen Fields, Jr. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields, Jr. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L12/66 ,  G06F3/00 ,  G06F12/00

CPC分类号： G06F15/7842

摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。

公开(公告)号：US07752369B2

公开(公告)日：2010-07-06

申请号：US12118211

申请日：2008-05-09

申请人： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

发明人： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

IPC分类号： G06F13/18

CPC分类号： G06F13/364

摘要： A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.

摘要翻译： 用于形式验证伪随机数生成器和使用随机优先级仲裁方案的仲裁器的有界公平属性的系统。 形式验证系统根据完整随机序列的数量确定仲裁者的请求授权延迟的上限。 形式验证系统还根据多个时钟周期确定由仲裁器使用的随机数发生器产生的随机数序列中的完整随机序列的长度的上限和下限。 然后，形式验证系统通过将仲裁者的请求授权延迟的上限与上限结合来确定在多个时钟周期方面仲裁系统的最差情况请求授权延迟范围 的完整随机序列的长度和完整随机序列的长度的下限。