公开(公告)号：US09063807B2

公开(公告)日：2015-06-23

申请号：US13594253

申请日：2012-08-24

Applicant: Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

Inventor： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

IPC: G06F7/58 ,  G06F13/14

CPC classification number: G06F7/58 ,  G06F13/14

Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.

Abstract translation: 随机数生成器包括公平校验器和校正模块，其确保在随机数发生器内将在预定时间段内的完整随机序列输出。

公开(公告)号：US07752369B2

公开(公告)日：2010-07-06

申请号：US12118211

申请日：2008-05-09

Applicant: Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

Inventor： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

IPC: G06F13/18

CPC classification number: G06F13/364

Abstract: A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.

Abstract translation: 用于形式验证伪随机数生成器和使用随机优先级仲裁方案的仲裁器的有界公平属性的系统。 形式验证系统根据完整随机序列的数量确定仲裁者的请求授权延迟的上限。 形式验证系统还根据多个时钟周期确定由仲裁器使用的随机数发生器产生的随机数序列中的完整随机序列的长度的上限和下限。 然后，形式验证系统通过将仲裁者的请求授权延迟的上限与上限结合来确定在多个时钟周期方面仲裁系统的最差情况请求授权延迟范围 的完整随机序列的长度和完整随机序列的长度的下限。

公开(公告)号：US08312071B2

公开(公告)日：2012-11-13

申请号：US12101734

申请日：2008-04-11

Applicant: Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

Inventor： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

IPC: G06F7/58

CPC classification number: G06F7/58 ,  G06F13/14

Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.

Abstract translation: 随机数生成器包括公平校验器和校正模块，其确保在随机数发生器内将在预定时间段内的完整随机序列输出。

公开(公告)号：US20090282178A1

公开(公告)日：2009-11-12

申请号：US12118211

申请日：2008-05-09

Applicant: Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

Inventor： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

IPC: G06F13/18

CPC classification number: G06F13/364

Abstract: A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.

Abstract translation: 用于形式验证伪随机数生成器和使用随机优先级仲裁方案的仲裁器的有界公平属性的系统。 形式验证系统根据完整随机序列的数量确定仲裁者的请求授权延迟的上限。 形式验证系统还根据多个时钟周期确定由仲裁器使用的随机数发生器产生的随机数序列中的完整随机序列的长度的上限和下限。 然后，形式验证系统通过将仲裁者的请求授权延迟的上限与上限结合来确定在多个时钟周期方面仲裁系统的最差情况请求授权延迟范围 的完整随机序列的长度和完整随机序列的长度的下限。

公开(公告)号：US08756543B2

公开(公告)日：2014-06-17

申请号：US13097171

申请日：2011-04-29

Applicant: Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

Inventor： Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/504 ,  G06F9/4498 ,  G06F17/5022

Abstract: A method, system, and computer program product for verification of a state transition machine (STM) are provided in the illustrative embodiments. The STM representing the operation of a circuit configured to perform a computation is received. A segment of the STM is selected from a set of segments of the STM. A set of properties of the segment is determined. The set of properties is translated into a hardware description to form a translation. The segment is verified by verifying whether all relationships between a pre-condition and a post condition in the translation hold true for any set of inputs and any initial state of a hardware design under test. A verification result for the segment is generated. Verification results for each segment in the set of segments are combined to generate a verification result for the STM.

Abstract translation: 在说明性实施例中提供了用于验证状态转换机（STM）的方法，系统和计算机程序产品。 接收表示被配置为执行计算的电路的操作的STM。 从STM的一组段中选择STM的一段。 确定该段的一组属性。 该属性集被翻译成硬件描述以形成一个翻译。 通过验证翻译中的前提条件和后期条件之间的所有关系是否适用于任何一组输入以及所测试的硬件设计的任何初始状态来验证该段。 生成段的验证结果。 组合段中每个段的验证结果，以生成STM的验证结果。

公开(公告)号：US08397189B2

公开(公告)日：2013-03-12

申请号：US13097193

申请日：2011-04-29

Applicant: Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

Inventor： Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

IPC: G06F9/455

CPC classification number: G06F17/504

Abstract: A method, system, and computer program product for improved model checking for verification of a state transition machine (STM) are provided. A hardware design under test and a property to be verified are received. A level (k) of induction proof needed for the verification is determined. A circuit representation of the property using the hardware design under test for k base cases is configured for checking that the circuit representation holds true for the property for each of the k base cases, and for testing an induction without hypothesis by testing whether the property holds true after k clock cycles starting from a randomized state, where induction without hypothesis is performed by omitting a test whether the property holds true for the next cycle after the property holds for k successive cycles. The induction proof of the property using the hardware design under test by induction without hypothesis is produced.

Abstract translation: 提供了一种用于改进状态转换机（STM）验证的模型检查的方法，系统和计算机程序产品。 收到被测试的硬件设计和待验证的属性。 确定验证所需的感应等级（k）。 配置用于k个基本情况的使用被测硬件设计的属性的电路表示被配置用于检查电路表示对于每个k个基本情况的属性是否成立，以及通过测试属性是否保持来测试没有假设的感应 在从随机化状态开始的k个时钟周期之后为真，其中通过省略在k个连续循环的该属性成立后的下一个周期的属性是否成立的情况下执行无假设的诱导。 产生使用通过没有假设的感应的被测硬件设计的属性的感应证明。

公开(公告)号：US20120096204A1

公开(公告)日：2012-04-19

申请号：US12906495

申请日：2010-10-18

Applicant: Gadiel Auerbach ,  Fady Copty ,  David J. Levitt ,  Viresh Paruthi

Inventor： Gadiel Auerbach ,  Fady Copty ,  David J. Levitt ,  Viresh Paruthi

IPC: G06F13/37

CPC classification number: G06F13/364

Abstract: A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a set of input ports. Responsive to the first predetermined time period expiring before the processor determines whether the random priority-based arbiter is blocking, a determination is made as to whether the random priority-based arbiter is blocking one of the set of output ports or the set of input ports within a second predetermined time period using the random seed and at least one of property strengthening or underapproximation. Responsive to the processor determining that the random priority-based arbiter satisfies a non-blocking specification such that not one of the set of output ports or the set of input ports is blocked within the second predetermined time period, the random priority-based arbiter is validated as satisfying the non-blocking specification.

Abstract translation: 提供了一种正式验证随机优先级仲裁器的机制。 确定随机优先级仲裁器是否阻塞一组输出端口或一组输入端口中的一个。 响应于在处理器确定基于随机优先级的仲裁器是否阻塞之前到期的第一预定时间段，确定基于随机优先级的仲裁器是否阻塞该组输出端口或输入端口组中的一个 在第二预定时间段内使用所述随机种子和性能加强或不足近似中的至少一种。 响应于所述处理器确定所述基于随机优先级的仲裁器满足非阻塞规范，使得所述一组输出端口或所述一组输入端口中的一个在所述第二预定时间段内被阻止，所述基于随机优先级的仲裁器是 验证满足非阻塞规范。

公开(公告)号：US08141048B2

公开(公告)日：2012-03-20

申请号：US11677652

申请日：2007-02-22

Applicant: Jason R. Baumgartner ,  Ali S. El-Zein ,  Viresh Paruthi ,  Fadi A. Zaraket

Inventor： Jason R. Baumgartner ,  Ali S. El-Zein ,  Viresh Paruthi ,  Fadi A. Zaraket

IPC: G06F9/44 ,  G06F9/455

CPC classification number: G06F8/43

Abstract: A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system. The sequential logic representation is formed by reference to a Hardware Description Language (HDL) library. Then, the sequential logic representation is transformed into a gate-level sequential logic representation. Following the transforming, the software system is verified based upon the gate-level sequential logic representation. Following verification, results of verification of the software system are output.

Abstract translation: 验证软件系统的方法包括接收使用高级建模语言描述的软件系统的描述，并且响应于此，解析描述并构造抽象语法图。 抽象语法图被转换成软件系统的顺序逻辑表示。 通过参考硬件描述语言（HDL）库形成顺序逻辑表示。 然后，顺序逻辑表示被转换成门级顺序逻辑表示。 在变换之后，基于门级顺序逻辑表示验证软件系统。 验证后，输出软件系统的验证结果。

公开(公告)号：US08015523B2

公开(公告)日：2011-09-06

申请号：US12392278

申请日：2009-02-25

Applicant: Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

Inventor： Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/505 ,  G06F17/504

Abstract: Methods and systems are provided for sequential netlist reduction through trace-containment for a circuitry design netlist by first identifying a cut of the netlist and enumerating a set of mismatch traces. Perform time-bounded unfolding of a cofactored version of the cut to reflect the sequential cofactor for a specific input i and temporal uncorrelation constraints for the set of inputs ‘J’. Determine whether there is trace containment by performing equivalence checking with respect to the cut of the netlist under temporal uncorrelation constraints for the set of inputs ‘J’. In response to detecting trace containment, simplify the netlist by merging the input ‘i’ to a constant.

Abstract translation: 提供方法和系统，用于通过电路设计网表的跟踪容纳来顺序的网表减少，首先识别网表的剪切并列举一组不匹配的跟踪。 执行切片的辅助版本的时间限制展开，以反映特定输入i的顺序辅因子和输入集合J'的时间非相关约束。 通过对输入集合J'的时间不相关约束执行相对于网表的切分的等价性检查来确定是否存在跟踪容纳。 响应检测跟踪容纳，通过将输入'i'合并为常数来简化网表。

公开(公告)号：US07853917B2

公开(公告)日：2010-12-14

申请号：US11963267

申请日：2007-12-21

Applicant: Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Oliver Weber

Inventor： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Oliver Weber

IPC: G06H17/50

CPC classification number: G06F17/30958 ,  G06F17/504 ,  Y10S707/99942

Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.

Abstract translation: 公开了一种用于在使用动态资源约束和交织的深度优先搜索和修改的宽度优先搜索时间表的数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。 该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。 然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定 使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。 响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。 响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。