公开(公告)号：US11670439B2

公开(公告)日：2023-06-06

申请号：US17499594

申请日：2021-10-12

Applicant: Microchip Technology incorporated

Inventor： Yaojian Leng

IPC: H01C7/00 ,  H01C17/232 ,  H01L23/522 ,  H01C17/12 ,  H01L49/02

CPC classification number: H01C7/006 ,  H01C17/12 ,  H01C17/232 ,  H01L23/5228 ,  H01L28/24

Abstract: A damascene method for manufacturing a thin film resistor (TFR) module is provided. A pair of heads are formed spaced apart from each other. A dielectric region is deposited over the pair of heads, and an opening extending over both heads is formed in the dielectric region. A TFR layer is deposited over the dielectric region and extending into the opening to define a cup-shaped TFR layer structure including (a) a laterally-extending TFR element base conductively connected to both heads and (b) vertical ridges extending upwardly from the laterally-extending TFR element base. A high density plasma (HDP) ridge removal process is performed to remove or shorten the vertical ridges from the cup-shaped TFR layer structure, thereby defining a TFR element having removed or shorted vertical ridges. The removal or shortening of the vertical ridges may improve the temperature coefficient of resistance (TCR) characteristic of the TFR element.

公开(公告)号：US20230079474A1

公开(公告)日：2023-03-16

申请号：US17992142

申请日：2022-11-22

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

公开(公告)号：US20230013766A1

公开(公告)日：2023-01-19

申请号：US17499594

申请日：2021-10-12

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01C7/00 ,  H01L49/02 ,  H01C17/12 ,  H01L23/522 ,  H01C17/232

Abstract: A damascene method for manufacturing a thin film resistor (TFR) module is provided. A pair of heads are formed spaced apart from each other. A dielectric region is deposited over the pair of heads, and an opening extending over both heads is formed in the dielectric region. A TFR layer is deposited over the dielectric region and extending into the opening to define a cup-shaped TFR layer structure including (a) a laterally-extending TFR element base conductively connected to both heads and (b) vertical ridges extending upwardly from the laterally-extending TFR element base. A high density plasma (HDP) ridge removal process is performed to remove or shorten the vertical ridges from the cup-shaped TFR layer structure, thereby defining a TFR element having removed or shorted vertical ridges. The removal or shortening of the vertical ridges may improve the temperature coefficient of resistance (TCR) characteristic of the TFR element.

公开(公告)号：US20220399352A1

公开(公告)日：2022-12-15

申请号：US17409883

申请日：2021-08-24

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L27/11507 ,  H01L49/02

Abstract: Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).

公开(公告)号：US20220270968A1

公开(公告)日：2022-08-25

申请号：US17233311

申请日：2021-04-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/525

Abstract: An electronic fuse (e-fuse) module may be formed in an integrated circuit device. The e-fuse module may include a pair of metal e-fuse terminals (e.g., copper terminals) and an e-fuse element formed directly on the metal e-fuse terminals to define a conductive path between the pair of metal e-fuse terminals through the e-fuse element. The metal e-fuse terminals may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The e-fuse element may be formed by depositing and patterning a diffusion barrier layer over the metal e-fuse terminals and interconnect elements formed in the metal interconnect layer. The e-fuse element may be formed from a material that provides a barrier against metal diffusion (e.g., copper diffusion) from each of the metal e-fuse terminals and interconnect elements. For example, the e-fuse element may be formed from titanium tungsten (TiW) or titanium tungsten nitride (TiW2N).

公开(公告)号：US20220165530A1

公开(公告)日：2022-05-26

申请号：US17233367

申请日：2021-04-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01H85/06 ,  H01L23/525 ,  H01H69/02

Abstract: An electronic fuse (e-fuse) module may be formed in copper interconnect in an integrated circuit device. A pair of e-fuse terminals may be formed by forming a pair of spaced-apart e-fuse terminal structures (e.g., copper damascene structures) and forming a conductive barrier region on each e-fuse terminal structure. The barrier regions may be formed by displacement plating a conductive barrier layer, e.g., comprising CoWP, CoWB, Pd, CoP, Ni, Co, or Ni—Co alloy, on each e-fuse terminal structure. An e-fuse element, e.g., comprising NiCr, TiW, TiWN, or Al, may be formed on the barrier regions of the pair of e-fuse terminals to define a conductive path between the pair of e-fuse terminal structures through the e-fuse element and through the barrier region on each e-fuse terminal structure. The barrier regions may protect the e-fuse terminal structures (e.g., copper structures) from corrosion and/or diffusion.

公开(公告)号：US20220130753A1

公开(公告)日：2022-04-28

申请号：US17306019

申请日：2021-05-03

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/67 ,  H01L49/02 ,  H01L23/528

Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.

公开(公告)号：US10553336B2

公开(公告)日：2020-02-04

申请号：US16034423

申请日：2018-07-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Greg Stom

IPC: H01C17/07 ,  H01C17/075 ,  H01C7/00 ,  H01C17/28 ,  H01C17/00 ,  H01C1/142

Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure is provided. A TFR trench may be formed in an oxide layer. A resistive TFR layer may be deposited over the structure and extending into the trench. Portions of the TFR layer outside the trench may be removed by CMP to define a TFR element including a laterally-extending TFR bottom region and a plurality of TFR ridges extending upwardly from the laterally-extending TFR bottom region. At least one CMP may be performed to remove all or portions of the oxide layer and at least a partial height of the TFR ridges. A pair of spaced-apart metal interconnects may then be formed over opposing end regions of the TFR element, wherein each metal interconnect contacts a respective upwardly-extending TFR ridge, to thereby define a resistor between the metal interconnects via the TFR element.

公开(公告)号：US20190392967A1

公开(公告)日：2019-12-26

申请号：US16034423

申请日：2018-07-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Greg Stom

IPC: H01C17/075 ,  H01C7/00 ,  H01C1/142 ,  H01C17/00 ,  H01C17/28

Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure is provided. A TFR trench may be formed in an oxide layer. A resistive TFR layer may be deposited over the structure and extending into the trench. Portions of the TFR layer outside the trench may be removed by CMP to define a TFR element including a laterally-extending TFR bottom region and a plurality of TFR ridges extending upwardly from the laterally-extending TFR bottom region. At least one CMP may be performed to remove all or portions of the oxide layer and at least a partial height of the TFR ridges. A pair of spaced-apart metal interconnects may then be formed over opposing end regions of the TFR element, wherein each metal interconnect contacts a respective upwardly-extending TFR ridge, to thereby define a resistor between the metal interconnects via the TFR element.

公开(公告)号：US12272639B2

公开(公告)日：2025-04-08

申请号：US17719548

申请日：2022-04-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/52 ,  H01F17/00 ,  H01F27/28 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10D1/20

Abstract: A device includes (a) an integrated inductor having an inductor wire and (b) a metal interconnect arrangement, both formed in an integrated circuit layer stack of alternating metal layers and via layers. At least a portion of the inductor wire is defined by an inductor element stack including multiple metal layer inductor elements formed in multiple respective metal layers, and multiple via layer inductor elements formed in multiple respective via layers and conductively connected to the metal layer inductor elements. Each via layer inductor element has a length of at least 1 μm in each of two lateral directions orthogonal to each other and perpendicular to the vertical direction. The metal interconnect arrangement includes metal layer interconnect elements formed in the respective metal layers, and interconnect vias formed in the respective via layers.