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公开(公告)号：US12205910B2
公开(公告)日：2025-01-21
申请号：US18141621
申请日：2023-05-01
Applicant: Microchip Technology Incorporated
Inventor： Justin Sato , Bomy Chen , Yaojian Leng , Gerald Marsico , Julius Kovats
Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.
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公开(公告)号：US12205885B2
公开(公告)日：2025-01-21
申请号：US18218197
申请日：2023-07-05
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng , Justin Sato
IPC: H01L23/522 , H01L21/66 , H01L21/67 , H01L23/528 , H01L49/02
Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.
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公开(公告)号：US12021115B2
公开(公告)日：2024-06-25
申请号：US17749367
申请日：2022-05-20
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
CPC classification number: H01L28/91 , H01L28/92 , H10B12/038 , H10B12/0387 , H10B12/37 , H01L28/75
Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. A dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup.
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公开(公告)号：US12010932B2
公开(公告)日：2024-06-11
申请号：US17379181
申请日：2021-07-19
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
CPC classification number: H10N70/841 , H10N70/066 , H10N70/24 , H10N70/245 , H10N70/826 , H10N70/8833
Abstract: Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The MIM structure of the RRAM cell may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped insulator. The cup-shaped bottom electrode, or a component thereof (in the case of a multi-layer bottom electrode) may be formed concurrent with interconnect vias, e.g., by deposition of tungsten or other conformal metal.
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公开(公告)号：US20230395649A1
公开(公告)日：2023-12-07
申请号：US17856183
申请日：2022-07-01
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L49/02 , H01L23/522 , H01L21/768
CPC classification number: H01L28/91 , H01L23/5223 , H01L23/5226 , H01L21/76802
Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode, an insulator cup formed on the bottom electrode, a top electrode formed in an opening defined by the insulator cup, a top electrode connection element electrically connected to the top electrode, a vertically-extending bottom electrode contact electrically connected to the bottom electrode, and a bottom electrode connection element electrically connected to the vertically-extending bottom electrode contact. The bottom electrode is formed in a lower metal layer. The insulator cup is formed in a tub opening in a dielectric region and includes a laterally extending insulator cup base formed on the bottom electrode and a vertically-extending insulator cup sidewall extending upwardly from the laterally extending insulator cup base. The top electrode connection element and bottom electrode connection element are formed in an upper metal layer.
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Patent Agency Ranking
公开(公告)号：US20230392992A1
公开(公告)日：2023-12-07
申请号：US18120093
申请日：2023-03-10
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
Abstract: A system includes a metal tub structure formed in an integrated circuit (IC) structure, a first metal component, and a second metal component. The first metal component is formed from a first metal. The first metal component is formed in an opening defined by the metal tub structure, and includes a first metal first junction element, a first metal second junction element, and a first metal bridge electrically connected to the first metal first junction element and the first metal second junction element. The second metal component is formed from a second metal different than the first metal, and includes a second metal first junction element electrically connected to the first metal first junction element to define a first thermocouple junction, and a second metal second junction element electrically connected to the first metal second junction element to define a second thermocouple junction.
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公开(公告)号：US11769722B2
公开(公告)日：2023-09-26
申请号：US17992142
申请日：2022-11-22
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L23/522 , H01L49/02 , H01L21/768 , H01L23/00 , H01L23/532
CPC classification number: H01L23/5223 , H01L21/7687 , H01L21/76816 , H01L21/76873 , H01L23/53228 , H01L24/05 , H01L24/06 , H01L28/60 , H01L23/53238 , H01L2224/0557 , H01L2224/05624
Abstract: A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.
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公开(公告)号：US11735516B2
公开(公告)日：2023-08-22
申请号：US17306019
申请日：2021-05-03
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng , Justin Sato
IPC: H01L23/522 , H01L21/66 , H01L23/528 , H01L49/02 , H01L21/67
CPC classification number: H01L23/5223 , H01L21/67259 , H01L22/20 , H01L22/34 , H01L23/5226 , H01L23/5283 , H01L28/40
Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.
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公开(公告)号：US11682641B2
公开(公告)日：2023-06-20
申请号：US17163645
申请日：2021-02-01
Applicant: Microchip Technology Incorporated
Inventor： Justin Sato , Bomy Chen , Yaojian Leng , Gerald Marsico , Julius Kovats
CPC classification number: H01L24/05 , H01L24/03 , H01L24/08 , H01L24/89 , H01L2224/0361 , H01L2224/05557 , H01L2224/05578 , H01L2224/05639 , H01L2224/05724 , H01L2224/05839 , H01L2224/08225 , H01L2224/80895
Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.
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公开(公告)号：US11670583B2
公开(公告)日：2023-06-06
申请号：US17117288
申请日：2020-12-10
Applicant: Microchip Technology incorporated
Inventor： Yaojian Leng , Justin Sato
IPC: H01L23/522 , H01L23/532 , H01F27/32 , H01F27/28 , H01L49/02
CPC classification number: H01L23/5227 , H01F27/2823 , H01F27/32 , H01L23/5329 , H01L23/53223 , H01L23/53238 , H01L28/10
Abstract: A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.
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