公开(公告)号：US20240330190A1

公开(公告)日：2024-10-03

申请号：US18737526

申请日：2024-06-07

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  David Andrew Roberts ,  Patrick Michael Sheridan ,  Lukasz Burzawa

IPC: G06F12/0882 ,  G06F12/06

CPC classification number: G06F12/0882 ,  G06F12/0646

Abstract: Disclosed in some examples are improved address prediction and memory preloading that leverages next-delta prediction and/or far-delta prediction for scheduling using a DNN. Previous memory access sequence data that identify one or more memory addresses previously accessed by one or more processors of a system may be processed and then converted into a sequence of delta values. The sequence of delta values are then mapped to one or more classes that are then input to a DNN. The DNN then outputs a predicted future class identifier sequence that represents addresses that the DNN predicts will be accessed by the processor in the future. The predicted future class identifier sequence is then converted back to a predicted delta value sequence and back into a set of one or more predicted addresses.

公开(公告)号：US20240069783A1

公开(公告)日：2024-02-29

申请号：US17897886

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Andrew Roberts

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/061 ,  G06F3/0679

Abstract: A system includes a memory device and a processing device coupled to the memory device, and the processing device is to perform operations including determining, by monitoring accesses to the memory device, a plurality of values of one or more memory usage statistics reflecting memory usage by a plurality of requestors connected to the memory sub-system; generating memory usage data by processing the plurality of values of the one or more memory usage statistics; and transmitting, to a requestor of the plurality of requestors, the memory usage data.

公开(公告)号：US11847059B2

公开(公告)日：2023-12-19

申请号：US17809136

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G11C5/06 ,  G06F12/06 ,  G01R31/317 ,  G06F11/10 ,  G06F12/0882 ,  G06F12/0868 ,  G06F9/54 ,  G06F11/30 ,  G06F9/50

CPC classification number: G06F12/0882 ,  G06F9/5016 ,  G06F9/546 ,  G06F11/1004 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/06 ,  G06F12/0868 ,  G11C5/066 ,  G01R31/31713

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

公开(公告)号：US20230393783A1

公开(公告)日：2023-12-07

申请号：US17831270

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Nabeel Meeramohideen Mohamed ,  Steven Andrew Moyer ,  David Andrew Roberts

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for access heatmap generation at a memory device are described. In some examples, a memory device may maintain a register for tracking access operation occurrence, for which access operations of an address of the memory device may be mapped to multiple fields of the register. In some cases, in response to a first access operation performed on a first address of the memory device, the memory device may increment a first field and a second field of the register and, in response to a second access operation performed on a second address of the memory device, the memory device may increment the first field and a third field of the register. In some examples, the memory device may maintain a second register having a set of fields that each indicate a respective address for which an access occurrence satisfies a threshold.

公开(公告)号：US11836084B2

公开(公告)日：2023-12-05

申请号：US17809126

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G11C5/06 ,  G06F12/06 ,  G06F11/10 ,  G06F12/0882 ,  G06F12/0868 ,  G06F9/54 ,  G06F11/30 ,  G06F9/50 ,  G01R31/317

CPC classification number: G06F12/0882 ,  G06F9/5016 ,  G06F9/546 ,  G06F11/1004 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/06 ,  G06F12/0868 ,  G11C5/066 ,  G01R31/31713

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

公开(公告)号：US20230088638A1

公开(公告)日：2023-03-23

申请号：US17820531

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/06

Abstract: Described apparatuses and methods track access metadata pertaining to activity within respective address ranges. The access metadata can be used to inform prefetch operations within the respective address ranges. The prefetch operations may involve deriving access patterns from access metadata covering the respective ranges. Suitable address range sizes for accurate pattern detection, however, can vary significantly from region to region of the address space based on, inter alia, workloads produced by programs utilizing the regions. Advantageously, the described apparatuses and methods can adapt the address ranges covered by the access metadata for improved prefetch performance. A data structure may be used to manage the address ranges in which access metadata are tracked. The address ranges can be adapted to improve prefetch performance through low-overhead operations implemented within the data structure. The data structure can encode hierarchical relationships that ensure the resulting address ranges are distinct.

公开(公告)号：US20230060587A1

公开(公告)日：2023-03-02

申请号：US17836529

申请日：2022-06-09

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  David Boles ,  David Andrew Roberts

IPC: G06F3/06

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allows an application thread to indicate an undo logging operation when calculations are beginning that may need to be rolled back if a crash or other failure occurs. During the undo logging operation, memory writes an identified memory are done to a copy and the original value is preserved. If the undo logging operation is committed, then the copy becomes the correct value and may then be subsequently used in place of the original, or the value stored in the copy is copied to the original. If the undo logging operation is abandoned, the copy is not preserved and the value goes back to the original.

公开(公告)号：US11586361B2

公开(公告)日：2023-02-21

申请号：US17663609

申请日：2022-05-16

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: Described apparatuses and methods control a voltage or a temperature of a memory domain to balance memory performance and energy use. In some aspects, an adaptive controller monitors memory performance metrics of a host processor that correspond to commands made to a memory domain of a memory system, including one operating at cryogenic temperatures. Based on the memory performance metrics, the adaptive controller can determine memory performance demand of the host processor, such as latency demand or bandwidth demand, for the memory domain. The adaptive controller may alter, using the determined performance demand, a voltage or a temperature of the memory domain to enable memory access performance that is tailored to meet the demand of the host processor. By so doing, the adaptive controller can manage various settings of the memory domain to address short- or long-term changes in memory performance demand.

公开(公告)号：US20230051103A1

公开(公告)日：2023-02-16

申请号：US17403366

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Aliasger Tayeb Zaidy

IPC: G06F3/06 ,  G06N3/04

Abstract: Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to predict a schedule for migrating data between memory devices, which can be part of a memory sub-system.

公开(公告)号：US20220327059A1

公开(公告)日：2022-10-13

申请号：US17809126

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0882 ,  G06F12/0868 ,  G06F9/54 ,  G06F11/10 ,  G06F11/30 ,  G06F9/50 ,  G11C5/06

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.