公开(公告)号：US20200176059A1

公开(公告)日：2020-06-04

申请号：US16205755

申请日：2018-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luigi Pilolli ,  Agatino Massimo Maccarrone ,  Hoon Choi ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: G11C16/10 ,  H03M9/00 ,  G11C16/04 ,  G11C16/32

Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.

公开(公告)号：US10387048B2

公开(公告)日：2019-08-20

申请号：US16006192

申请日：2018-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G11C16/32 ,  G06F3/06 ,  G11C16/26 ,  G06F12/0802 ,  G11C7/10 ,  G11C7/22 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US09659631B2

公开(公告)日：2017-05-23

申请号：US14602084

申请日：2015-01-21

Applicant: MICRON TECHNOLOGY, INC

Inventor： Onegyun Na ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

IPC: G11C7/00 ,  G11C7/22 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C11/4074 ,  G11C2207/063 ,  G11C2207/2281

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.