MEMORY DECISION FEEDBACK EQUALIZER TESTING
    11.
    发明申请

    公开(公告)号:US20190097846A1

    公开(公告)日:2019-03-28

    申请号:US15714818

    申请日:2017-09-25

    Abstract: A device includes one or more memory banks configured to store data. The device also includes a data receiver configured to receive distorted input data as part of a data stream, apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, and generate the data by applying the correction factor to the distorted data. The device further includes a test circuit internal to the device, wherein the test circuit is configured to generate the data stream.

    Multi-mode voltage pump and control

    公开(公告)号:US11824441B2

    公开(公告)日:2023-11-21

    申请号:US17840434

    申请日:2022-06-14

    CPC classification number: H02M3/07 G11C5/145 G11C17/18 H03K19/20 G11C11/4074

    Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.

    APPARATUSES AND METHODS INCLUDING DICE LATCHES IN A SEMICONDUCTOR DEVICE

    公开(公告)号:US20230343376A1

    公开(公告)日:2023-10-26

    申请号:US18335385

    申请日:2023-06-15

    CPC classification number: G11C7/1087

    Abstract: According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.

    MULTI-MODE VOLTAGE PUMP AND CONTROL

    公开(公告)号:US20210359598A1

    公开(公告)日:2021-11-18

    申请号:US16321769

    申请日:2018-12-04

    Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.

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