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公开(公告)号：US10783937B2
公开(公告)日：2020-09-22
申请号：US16723570
申请日：2019-12-20
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , Jennifer E. Taylor
Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.
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公开(公告)号：US10447508B2
公开(公告)日：2019-10-15
申请号：US15872124
申请日：2018-01-16
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , Jennifer E. Taylor
IPC: H04L25/03
Abstract: A device includes a first bias level generator to generate a first bias level of a plurality of bias levels and transmit the bias level having a first voltage value, a second bias level generator to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value. The device also includes a voltage divider that interpolates a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level and supplies a selected bias level of the plurality of bias levels a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.
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公开(公告)号：US20190280906A1
公开(公告)日：2019-09-12
申请号：US15914913
申请日：2018-03-07
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor
Abstract: A continuous time linear equalization (CTLE) system is provided. The CTLE system includes a first adjustable circuit comprising a first adjustable resistive-capacitive (RC) source degeneration circuit and a first differential amplifier stage circuit. The CTLE system also includes a second adjustable circuit electrically coupled to the first adjustable circuit and configured to adjust a frequency suppression of a data signal received by the CTLE system. The CTLE system is configured to provide a gain-versus-frequency curve for the data signal based on adjustments to the first adjustable circuit, adjustments to the second adjustable circuit, or a combination thereof.
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公开(公告)号：US20190097846A1
公开(公告)日：2019-03-28
申请号：US15714818
申请日：2017-09-25
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , Jennifer E. Taylor , Liang Liu
IPC: H04L25/03
Abstract: A device includes one or more memory banks configured to store data. The device also includes a data receiver configured to receive distorted input data as part of a data stream, apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, and generate the data by applying the correction factor to the distorted data. The device further includes a test circuit internal to the device, wherein the test circuit is configured to generate the data stream.
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公开(公告)号：US20240420790A1
公开(公告)日：2024-12-19
申请号：US18635869
申请日：2024-04-15
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Eric J. Stave , Timothy M. Hollis , Chulkyu Lee , Chris Gregory Holub
Abstract: Systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. The received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. A first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. The first received bit is also latched in error evaluation circuitry as a second latched bit. The second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. The self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.
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Patent Agency Ranking
公开(公告)号：US20230403184A1
公开(公告)日：2023-12-14
申请号：US18214876
申请日：2023-06-27
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Raghukiran Sreeramaneni
CPC classification number: H04L25/03267 , H04L25/03949 , H04L25/06 , H04L25/062 , H04L25/03057
Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.
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公开(公告)号：US20200280467A1
公开(公告)日：2020-09-03
申请号：US16878288
申请日：2020-05-19
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Raghukiran Sreeramaneni
Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
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公开(公告)号：US10666470B2
公开(公告)日：2020-05-26
申请号：US16289517
申请日：2019-02-28
Applicant: Micron Technology, Inc.
Inventor： Jennifer E. Taylor , Raghukiran Sreeramaneni
IPC: H04L25/03 , G11C11/401 , G11C7/10
Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
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公开(公告)号：US10529391B2
公开(公告)日：2020-01-07
申请号：US16517165
申请日：2019-07-19
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , Jennifer E. Taylor
Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.
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公开(公告)号：US10373659B2
公开(公告)日：2019-08-06
申请号：US15850965
申请日：2017-12-21
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , Jennifer E. Taylor
Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.
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