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    Signed division in memory
    11.
    发明授权
    Signed division in memory 有权

    公开(公告)号：US10042608B2

    公开(公告)日：2018-08-07

    申请号：US15152266

    申请日：2016-05-11

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G06F7/535 ,  G06F5/01 ,  G11C7/00

    CPC classification number: G06F7/535 ,  G06F5/01 ,  G06F2205/00 ,  G06F2207/535 ,  G11C7/00 ,  G11C7/065 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4091

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

    Data shift by elements of a vector in memory
    13.
    发明授权
    Data shift by elements of a vector in memory 有权

    公开(公告)号：US09601166B2

    公开(公告)日：2017-03-21

    申请号：US15060222

    申请日：2016-03-03

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C7/10 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4096

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

    Loop structure for operations in memory
    14.
    发明授权
    Loop structure for operations in memory 有权
    内存中操作的循环结构

    公开(公告)号：US09583163B2

    公开(公告)日：2017-02-28

    申请号：US15013269

    申请日：2016-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari ,  Kyle Wheeler

    IPC: G11C8/04 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

    CPC classification number: G11C7/1012 ,  G11C7/00 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/12 ,  G11C8/04 ,  G11C11/4091 ,  G11C11/4094

    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

    Abstract translation: 本公开的示例提供了与在存储器中执行的操作执行循环结构相关的装置和方法。 示例性装置还可以包括控制器，其被配置为使得感测电路经由环路结构遍历多个第一元件和多个第二元件，以使用多个第一元件和多个第二元件执行操作，其中a 与循环结构相关联的条件语句用于确定存储为迭代器掩码的多个比特中的至少一个是否具有特定的比特值。 示例性装置还可以包括可控制的感测电路，以在循环结构的每次迭代时使用迭代器掩码执行移位操作，并且在循环结构的每次迭代时使用迭代器掩码执行AND运算。

    DATA SHIFT BY ELEMENTS OF A VECTOR IN MEMORY
    15.
    发明申请
    DATA SHIFT BY ELEMENTS OF A VECTOR IN MEMORY 有权
    通过记忆体中的矢量的元素进行数据移动

    公开(公告)号：US20160267951A1

    公开(公告)日：2016-09-15

    申请号：US15060222

    申请日：2016-03-03

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C7/06 ,  G11C7/10

    CPC classification number: G11C7/1036 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

    Abstract translation: 本公开的示例提供了用于在存储器中执行移位操作的装置和方法。 一个示例性方法包括：执行移位操作，该第一元素存储在耦合到第一存取线的第一组存储器单元和存储器阵列的多条感测线以及存储在耦合到第一存储器单元的第二存储单元组中的第二元件 第二访问线和存储器阵列的感测线的数量。 该方法可以包括通过执行不经由输入/输出（I / O）传送数据而执行的多个AND运算，OR运算，SHIFT运算和INVERT运算，来移动第一元素移动由第二元素限定的位数位置。 线。

    MEMORY SUB-SYSTEM EVENT LOG MANAGEMENT
    16.
    发明申请
    MEMORY SUB-SYSTEM EVENT LOG MANAGEMENT 有权

    公开(公告)号：US20230017942A1

    公开(公告)日：2023-01-19

    申请号：US17946885

    申请日：2022-09-16

    Applicant: Micron Technology, Inc.

    Inventor： Adam J. Hieb ,  Adam C. Guy ,  Sanjay Tiwari ,  Todd A. Marquart

    IPC: G06F3/06 ,  G06F11/07

    Abstract: A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.

    Span mask generation
    17.
    发明授权
    Span mask generation 有权

    公开(公告)号：US11437079B2

    公开(公告)日：2022-09-06

    申请号：US16835007

    申请日：2020-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/10

    Abstract: Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth.

    Multiplication operations in memory
    20.
    发明授权
    Multiplication operations in memory 有权

    公开(公告)号：US10713011B2

    公开(公告)日：2020-07-14

    申请号：US16564366

    申请日：2019-09-09

    Applicant: Micron Technology, Inc.

    Inventor： Sanjay Tiwari

    IPC: G06F7/523 ,  G11C7/10 ,  G11C11/4096

    Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

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